inject_fault.c File Reference

#include <linux/kvm_host.h>
#include <asm/kvm_emulate.h>
#include <asm/kvm_nested.h>
#include <asm/esr.h>

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Macros
#define	DFSR_FSC_EXTABT_LPAE   0x10
#define	DFSR_FSC_EXTABT_nLPAE   0x08
#define	DFSR_LPAE   BIT(9)
#define	TTBCR_EAE   BIT(31)

Functions
static void	pend_sync_exception (struct kvm_vcpu *vcpu)
static bool	match_target_el (struct kvm_vcpu *vcpu, unsigned long target)
static void	inject_abt64 (struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
static void	inject_undef64 (struct kvm_vcpu *vcpu)
static void	inject_undef32 (struct kvm_vcpu *vcpu)
static void	inject_abt32 (struct kvm_vcpu *vcpu, bool is_pabt, u32 addr)
void	kvm_inject_dabt (struct kvm_vcpu *vcpu, unsigned long addr)
void	kvm_inject_pabt (struct kvm_vcpu *vcpu, unsigned long addr)
void	kvm_inject_size_fault (struct kvm_vcpu *vcpu)
void	kvm_inject_undefined (struct kvm_vcpu *vcpu)
void	kvm_set_sei_esr (struct kvm_vcpu *vcpu, u64 esr)
void	kvm_inject_vabt (struct kvm_vcpu *vcpu)

Macro Definition Documentation

DFSR_FSC_EXTABT_LPAE

#define DFSR_FSC_EXTABT_LPAE   0x10

Definition at line 114 of file inject_fault.c.

DFSR_FSC_EXTABT_nLPAE

#define DFSR_FSC_EXTABT_nLPAE   0x08

Definition at line 115 of file inject_fault.c.

DFSR_LPAE

#define DFSR_LPAE   BIT(9)

Definition at line 116 of file inject_fault.c.

TTBCR_EAE

#define TTBCR_EAE   BIT(31)

Definition at line 117 of file inject_fault.c.

Function Documentation

inject_abt32()

static void inject_abt32 ( struct kvm_vcpu *  vcpu, bool  is_pabt, u32  addr  )

static

Definition at line 128 of file inject_fault.c.

{
    u64 far;
    u32 fsr;
 
    /* Give the guest an IMPLEMENTATION DEFINED exception */
    if (vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE) {
        fsr = DFSR_LPAE | DFSR_FSC_EXTABT_LPAE;
    } else {
        /* no need to shuffle FS[4] into DFSR[10] as its 0 */
        fsr = DFSR_FSC_EXTABT_nLPAE;
    }
 
    far = vcpu_read_sys_reg(vcpu, FAR_EL1);
 
    if (is_pabt) {
        kvm_pend_exception(vcpu, EXCEPT_AA32_IABT);
        far &= GENMASK(31, 0);
        far |= (u64)addr << 32;
        vcpu_write_sys_reg(vcpu, fsr, IFSR32_EL2);
    } else { /* !iabt */
        kvm_pend_exception(vcpu, EXCEPT_AA32_DABT);
        far &= GENMASK(63, 32);
        far |= addr;
        vcpu_write_sys_reg(vcpu, fsr, ESR_EL1);
    }
 
    vcpu_write_sys_reg(vcpu, far, FAR_EL1);
}

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inject_abt64()

static void inject_abt64 ( struct kvm_vcpu *  vcpu, bool  is_iabt, unsigned long  addr  )

static

Definition at line 57 of file inject_fault.c.

{
    unsigned long cpsr = *vcpu_cpsr(vcpu);
    bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
    u64 esr = 0;
 
    pend_sync_exception(vcpu);
 
    /*
     * Build an {i,d}abort, depending on the level and the
     * instruction set. Report an external synchronous abort.
     */
    if (kvm_vcpu_trap_il_is32bit(vcpu))
        esr |= ESR_ELx_IL;
 
    /*
     * Here, the guest runs in AArch64 mode when in EL1. If we get
     * an AArch32 fault, it means we managed to trap an EL0 fault.
     */
    if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
        esr |= (ESR_ELx_EC_IABT_LOW << ESR_ELx_EC_SHIFT);
    else
        esr |= (ESR_ELx_EC_IABT_CUR << ESR_ELx_EC_SHIFT);
 
    if (!is_iabt)
        esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
 
    esr |= ESR_ELx_FSC_EXTABT;
 
    if (match_target_el(vcpu, unpack_vcpu_flag(EXCEPT_AA64_EL1_SYNC))) {
        vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
        vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
    } else {
        vcpu_write_sys_reg(vcpu, addr, FAR_EL2);
        vcpu_write_sys_reg(vcpu, esr, ESR_EL2);
    }
}

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inject_undef32()

static void inject_undef32 ( struct kvm_vcpu *  vcpu )

static

Definition at line 119 of file inject_fault.c.

{
    kvm_pend_exception(vcpu, EXCEPT_AA32_UND);
}

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inject_undef64()

static void inject_undef64 ( struct kvm_vcpu *  vcpu )

static

Definition at line 95 of file inject_fault.c.

{
    u64 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
 
    pend_sync_exception(vcpu);
 
    /*
     * Build an unknown exception, depending on the instruction
     * set.
     */
    if (kvm_vcpu_trap_il_is32bit(vcpu))
        esr |= ESR_ELx_IL;
 
    if (match_target_el(vcpu, unpack_vcpu_flag(EXCEPT_AA64_EL1_SYNC)))
        vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
    else
        vcpu_write_sys_reg(vcpu, esr, ESR_EL2);
}

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kvm_inject_dabt()

void kvm_inject_dabt	(	struct kvm_vcpu *	vcpu,
		unsigned long	addr
	)

kvm_inject_dabt - inject a data abort into the guest @vcpu: The VCPU to receive the data abort @addr: The address to report in the DFAR

It is assumed that this code is called from the VCPU thread and that the VCPU therefore is not currently executing guest code.

Definition at line 166 of file inject_fault.c.

{
    if (vcpu_el1_is_32bit(vcpu))
        inject_abt32(vcpu, false, addr);
    else
        inject_abt64(vcpu, false, addr);
}

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kvm_inject_pabt()

void kvm_inject_pabt	(	struct kvm_vcpu *	vcpu,
		unsigned long	addr
	)

kvm_inject_pabt - inject a prefetch abort into the guest @vcpu: The VCPU to receive the prefetch abort @addr: The address to report in the DFAR

It is assumed that this code is called from the VCPU thread and that the VCPU therefore is not currently executing guest code.

Definition at line 182 of file inject_fault.c.

{
    if (vcpu_el1_is_32bit(vcpu))
        inject_abt32(vcpu, true, addr);
    else
        inject_abt64(vcpu, true, addr);
}

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kvm_inject_size_fault()

void kvm_inject_size_fault

(

struct kvm_vcpu *

vcpu

)

Definition at line 190 of file inject_fault.c.

{
    unsigned long addr, esr;
 
    addr  = kvm_vcpu_get_fault_ipa(vcpu);
    addr |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
 
    if (kvm_vcpu_trap_is_iabt(vcpu))
        kvm_inject_pabt(vcpu, addr);
    else
        kvm_inject_dabt(vcpu, addr);
 
    /*
     * If AArch64 or LPAE, set FSC to 0 to indicate an Address
     * Size Fault at level 0, as if exceeding PARange.
     *
     * Non-LPAE guests will only get the external abort, as there
     * is no way to describe the ASF.
     */
    if (vcpu_el1_is_32bit(vcpu) &&
        !(vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE))
        return;
 
    esr = vcpu_read_sys_reg(vcpu, ESR_EL1);
    esr &= ~GENMASK_ULL(5, 0);
    vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
}

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kvm_inject_undefined()

void kvm_inject_undefined

(

struct kvm_vcpu *

vcpu

)

kvm_inject_undefined - inject an undefined instruction into the guest @vcpu: The vCPU in which to inject the exception

It is assumed that this code is called from the VCPU thread and that the VCPU therefore is not currently executing guest code.

Definition at line 225 of file inject_fault.c.

{
    if (vcpu_el1_is_32bit(vcpu))
        inject_undef32(vcpu);
    else
        inject_undef64(vcpu);
}

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kvm_inject_vabt()

void kvm_inject_vabt

(

struct kvm_vcpu *

vcpu

)

kvm_inject_vabt - inject an async abort / SError into the guest @vcpu: The VCPU to receive the exception

It is assumed that this code is called from the VCPU thread and that the VCPU therefore is not currently executing guest code.

Systems with the RAS Extensions specify an imp-def ESR (ISV/IDS = 1) with the remaining ISS all-zeros so that this error is not interpreted as an uncategorized RAS error. Without the RAS Extensions we can't specify an ESR value, so the CPU generates an imp-def value.

Definition at line 251 of file inject_fault.c.

{
    kvm_set_sei_esr(vcpu, ESR_ELx_ISV);
}

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kvm_set_sei_esr()

void kvm_set_sei_esr	(	struct kvm_vcpu *	vcpu,
		u64	esr
	)

Definition at line 233 of file inject_fault.c.

{
    vcpu_set_vsesr(vcpu, esr & ESR_ELx_ISS_MASK);
    *vcpu_hcr(vcpu) |= HCR_VSE;
}

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match_target_el()

static bool match_target_el ( struct kvm_vcpu *  vcpu, unsigned long  target  )

static

Definition at line 52 of file inject_fault.c.

{
    return (vcpu_get_flag(vcpu, EXCEPT_MASK) == target);
}

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pend_sync_exception()

static void pend_sync_exception ( struct kvm_vcpu *  vcpu )

static

Definition at line 18 of file inject_fault.c.

{
    /* If not nesting, EL1 is the only possible exception target */
    if (likely(!vcpu_has_nv(vcpu))) {
        kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
        return;
    }
 
    /*
     * With NV, we need to pick between EL1 and EL2. Note that we
     * never deal with a nesting exception here, hence never
     * changing context, and the exception itself can be delayed
     * until the next entry.
     */
    switch(*vcpu_cpsr(vcpu) & PSR_MODE_MASK) {
    case PSR_MODE_EL2h:
    case PSR_MODE_EL2t:
        kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC);
        break;
    case PSR_MODE_EL1h:
    case PSR_MODE_EL1t:
        kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
        break;
    case PSR_MODE_EL0t:
        if (vcpu_el2_tge_is_set(vcpu))
            kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC);
        else
            kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
        break;
    default:
        BUG();
    }
}

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