vmx.h File Reference

#include <linux/kvm_host.h>
#include <asm/kvm.h>
#include <asm/intel_pt.h>
#include <asm/perf_event.h>
#include "capabilities.h"
#include "../kvm_cache_regs.h"
#include "posted_intr.h"
#include "vmcs.h"
#include "vmx_ops.h"
#include "../cpuid.h"
#include "run_flags.h"

Include dependency graph for vmx.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes
struct	vmx_msrs
struct	vmx_uret_msr
struct	pt_ctx
struct	pt_desc
union	vmx_exit_reason
struct	lbr_desc
struct	nested_vmx
struct	vcpu_vmx
struct	vcpu_vmx::msr_autoload
struct	vcpu_vmx::msr_autostore
struct	kvm_vmx

Macros
#define	MSR_TYPE_R   1
#define	MSR_TYPE_W   2
#define	MSR_TYPE_RW   3
#define	X2APIC_MSR(r)   (APIC_BASE_MSR + ((r) >> 4))
#define	MAX_NR_USER_RETURN_MSRS   4
#define	MAX_NR_LOADSTORE_MSRS   8
#define	RTIT_ADDR_RANGE   4
#define	PML_ENTITY_NUM   512
#define	MAX_POSSIBLE_PASSTHROUGH_MSRS   16
#define	__BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base)
#define	BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop)
#define	__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS    (VM_ENTRY_LOAD_DEBUG_CONTROLS)
#define	KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS    __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS
#define	KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS
#define	__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS
#define	KVM_REQUIRED_VMX_VM_EXIT_CONTROLS    __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS
#define	KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS
#define	KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL
#define	KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL
#define	__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL
#define	KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL    __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL
#define	KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL
#define	KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL   0
#define	KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL
#define	KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL   0
#define	KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL    (TERTIARY_EXEC_IPI_VIRT)
#define	BUILD_CONTROLS_SHADOW(lname, uname, bits)
#define	VMX_REGS_LAZY_LOAD_SET

Enumerations
enum	segment_cache_field {   SEG_FIELD_SEL = 0 , SEG_FIELD_BASE = 1 , SEG_FIELD_LIMIT = 2 , SEG_FIELD_AR = 3 ,   SEG_FIELD_NR = 4 }

Functions
void	vmx_vcpu_load_vmcs (struct kvm_vcpu *vcpu, int cpu, struct loaded_vmcs *buddy)
int	allocate_vpid (void)
void	free_vpid (int vpid)
void	vmx_set_constant_host_state (struct vcpu_vmx *vmx)
void	vmx_prepare_switch_to_guest (struct kvm_vcpu *vcpu)
void	vmx_set_host_fs_gs (struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, unsigned long fs_base, unsigned long gs_base)
int	vmx_get_cpl (struct kvm_vcpu *vcpu)
bool	vmx_emulation_required (struct kvm_vcpu *vcpu)
unsigned long	vmx_get_rflags (struct kvm_vcpu *vcpu)
void	vmx_set_rflags (struct kvm_vcpu *vcpu, unsigned long rflags)
u32	vmx_get_interrupt_shadow (struct kvm_vcpu *vcpu)
void	vmx_set_interrupt_shadow (struct kvm_vcpu *vcpu, int mask)
int	vmx_set_efer (struct kvm_vcpu *vcpu, u64 efer)
void	vmx_set_cr0 (struct kvm_vcpu *vcpu, unsigned long cr0)
void	vmx_set_cr4 (struct kvm_vcpu *vcpu, unsigned long cr4)
void	set_cr4_guest_host_mask (struct vcpu_vmx *vmx)
void	ept_save_pdptrs (struct kvm_vcpu *vcpu)
void	vmx_get_segment (struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
void	__vmx_set_segment (struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
u64	construct_eptp (struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level)
bool	vmx_guest_inject_ac (struct kvm_vcpu *vcpu)
void	vmx_update_exception_bitmap (struct kvm_vcpu *vcpu)
bool	vmx_nmi_blocked (struct kvm_vcpu *vcpu)
bool	vmx_interrupt_blocked (struct kvm_vcpu *vcpu)
bool	vmx_get_nmi_mask (struct kvm_vcpu *vcpu)
void	vmx_set_nmi_mask (struct kvm_vcpu *vcpu, bool masked)
void	vmx_set_virtual_apic_mode (struct kvm_vcpu *vcpu)
struct vmx_uret_msr *	vmx_find_uret_msr (struct vcpu_vmx *vmx, u32 msr)
void	pt_update_intercept_for_msr (struct kvm_vcpu *vcpu)
void	vmx_update_host_rsp (struct vcpu_vmx *vmx, unsigned long host_rsp)
void	vmx_spec_ctrl_restore_host (struct vcpu_vmx *vmx, unsigned int flags)
unsigned int	__vmx_vcpu_run_flags (struct vcpu_vmx *vmx)
bool	__vmx_vcpu_run (struct vcpu_vmx *vmx, unsigned long *regs, unsigned int flags)
int	vmx_find_loadstore_msr_slot (struct vmx_msrs *m, u32 msr)
void	vmx_ept_load_pdptrs (struct kvm_vcpu *vcpu)
void	vmx_disable_intercept_for_msr (struct kvm_vcpu *vcpu, u32 msr, int type)
void	vmx_enable_intercept_for_msr (struct kvm_vcpu *vcpu, u32 msr, int type)
u64	vmx_get_l2_tsc_offset (struct kvm_vcpu *vcpu)
u64	vmx_get_l2_tsc_multiplier (struct kvm_vcpu *vcpu)
gva_t	vmx_get_untagged_addr (struct kvm_vcpu *vcpu, gva_t gva, unsigned int flags)
static void	vmx_set_intercept_for_msr (struct kvm_vcpu *vcpu, u32 msr, int type, bool value)
void	vmx_update_cpu_dirty_logging (struct kvm_vcpu *vcpu)
static u8	vmx_get_rvi (void)
static unsigned long	vmx_l1_guest_owned_cr0_bits (void)
static __always_inline struct kvm_vmx *	to_kvm_vmx (struct kvm *kvm)
static __always_inline struct vcpu_vmx *	to_vmx (struct kvm_vcpu *vcpu)
static struct lbr_desc *	vcpu_to_lbr_desc (struct kvm_vcpu *vcpu)
static struct x86_pmu_lbr *	vcpu_to_lbr_records (struct kvm_vcpu *vcpu)
static bool	intel_pmu_lbr_is_enabled (struct kvm_vcpu *vcpu)
void	intel_pmu_cross_mapped_check (struct kvm_pmu *pmu)
int	intel_pmu_create_guest_lbr_event (struct kvm_vcpu *vcpu)
void	vmx_passthrough_lbr_msrs (struct kvm_vcpu *vcpu)
static __always_inline unsigned long	vmx_get_exit_qual (struct kvm_vcpu *vcpu)
static __always_inline u32	vmx_get_intr_info (struct kvm_vcpu *vcpu)
struct vmcs *	alloc_vmcs_cpu (bool shadow, int cpu, gfp_t flags)
void	free_vmcs (struct vmcs *vmcs)
int	alloc_loaded_vmcs (struct loaded_vmcs *loaded_vmcs)
void	free_loaded_vmcs (struct loaded_vmcs *loaded_vmcs)
void	loaded_vmcs_clear (struct loaded_vmcs *loaded_vmcs)
static struct vmcs *	alloc_vmcs (bool shadow)
static bool	vmx_has_waitpkg (struct vcpu_vmx *vmx)
static bool	vmx_need_pf_intercept (struct kvm_vcpu *vcpu)
static bool	is_unrestricted_guest (struct kvm_vcpu *vcpu)
bool	__vmx_guest_state_valid (struct kvm_vcpu *vcpu)
static bool	vmx_guest_state_valid (struct kvm_vcpu *vcpu)
void	dump_vmcs (struct kvm_vcpu *vcpu)
static int	vmx_get_instr_info_reg2 (u32 vmx_instr_info)
static bool	vmx_can_use_ipiv (struct kvm_vcpu *vcpu)

Macro Definition Documentation

__BUILD_VMX_MSR_BITMAP_HELPER

#define __BUILD_VMX_MSR_BITMAP_HELPER	(		rtype,
			action,
			bitop,
			access,
			base
	)

Value:

static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap,  \
                               u32 msr)            \
{                                          \
    int f = sizeof(unsigned long);                         \
                                           \
    if (msr <= 0x1fff)                             \
        return bitop##_bit(msr, bitmap + base / f);            \
    else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))               \
        return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \
    return (rtype)true;                            \
}

Definition at line 446 of file vmx.h.

__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL

#define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL

Value:

    (CPU_BASED_HLT_EXITING |                    \
     CPU_BASED_CR3_LOAD_EXITING |                   \
     CPU_BASED_CR3_STORE_EXITING |                  \
     CPU_BASED_UNCOND_IO_EXITING |                  \
     CPU_BASED_MOV_DR_EXITING |                 \
     CPU_BASED_USE_TSC_OFFSETTING |                 \
     CPU_BASED_MWAIT_EXITING |                  \
     CPU_BASED_MONITOR_EXITING |                    \
     CPU_BASED_INVLPG_EXITING |                 \
     CPU_BASED_RDPMC_EXITING |                  \
     CPU_BASED_INTR_WINDOW_EXITING)

Definition at line 519 of file vmx.h.

__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS

#define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS    (VM_ENTRY_LOAD_DEBUG_CONTROLS)

Definition at line 471 of file vmx.h.

__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS

#define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS

Value:

    (VM_EXIT_SAVE_DEBUG_CONTROLS |                  \
     VM_EXIT_ACK_INTR_ON_EXIT)

Definition at line 489 of file vmx.h.

BUILD_CONTROLS_SHADOW

#define BUILD_CONTROLS_SHADOW	(		lname,
			uname,
			bits
	)

Value:

static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val)          \
{                                               \
    if (vmx->loaded_vmcs->controls_shadow.lname != val) {                   \
        vmcs_write##bits(uname, val);                           \
        vmx->loaded_vmcs->controls_shadow.lname = val;                  \
    }                                           \
}                                               \
static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs)            \
{                                               \
    return vmcs->controls_shadow.lname;                         \
}                                               \
static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx)                \
{                                               \
    return __##lname##_controls_get(vmx->loaded_vmcs);                  \
}                                               \
static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val)      \
{                                               \
    BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname)));       \
    lname##_controls_set(vmx, lname##_controls_get(vmx) | val);             \
}                                               \
static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val)    \
{                                               \
    BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname)));       \
    lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);                \
}

Definition at line 585 of file vmx.h.

BUILD_VMX_MSR_BITMAP_HELPERS

#define BUILD_VMX_MSR_BITMAP_HELPERS	(		ret_type,
			action,
			bitop
	)

Value:

    __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read,  0x0)     \
    __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800)

Definition at line 458 of file vmx.h.

KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL

#define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL

Value:

    (CPU_BASED_RDTSC_EXITING |                  \
     CPU_BASED_TPR_SHADOW |                     \
     CPU_BASED_USE_IO_BITMAPS |                 \
     CPU_BASED_MONITOR_TRAP_FLAG |                  \
     CPU_BASED_USE_MSR_BITMAPS |                    \
     CPU_BASED_NMI_WINDOW_EXITING |                 \
     CPU_BASED_PAUSE_EXITING |                  \
     CPU_BASED_ACTIVATE_SECONDARY_CONTROLS |            \
     CPU_BASED_ACTIVATE_TERTIARY_CONTROLS)

Definition at line 542 of file vmx.h.

KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL

#define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL

Value:

    (PIN_BASED_VIRTUAL_NMIS |                   \
     PIN_BASED_POSTED_INTR |                    \
     PIN_BASED_VMX_PREEMPTION_TIMER)

Definition at line 514 of file vmx.h.

KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL

#define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL

Value:

    (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |          \
     SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |            \
     SECONDARY_EXEC_WBINVD_EXITING |                \
     SECONDARY_EXEC_ENABLE_VPID |                   \
     SECONDARY_EXEC_ENABLE_EPT |                    \
     SECONDARY_EXEC_UNRESTRICTED_GUEST |                \
     SECONDARY_EXEC_PAUSE_LOOP_EXITING |                \
     SECONDARY_EXEC_DESC |                      \
     SECONDARY_EXEC_ENABLE_RDTSCP |                 \
     SECONDARY_EXEC_ENABLE_INVPCID |                \
     SECONDARY_EXEC_APIC_REGISTER_VIRT |                \
     SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |             \
     SECONDARY_EXEC_SHADOW_VMCS |                   \
     SECONDARY_EXEC_ENABLE_XSAVES |                 \
     SECONDARY_EXEC_RDSEED_EXITING |                \
     SECONDARY_EXEC_RDRAND_EXITING |                \
     SECONDARY_EXEC_ENABLE_PML |                    \
     SECONDARY_EXEC_TSC_SCALING |                   \
     SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE |             \
     SECONDARY_EXEC_PT_USE_GPA |                    \
     SECONDARY_EXEC_PT_CONCEAL_VMX |                \
     SECONDARY_EXEC_ENABLE_VMFUNC |                 \
     SECONDARY_EXEC_BUS_LOCK_DETECTION |                \
     SECONDARY_EXEC_NOTIFY_VM_EXITING |             \
     SECONDARY_EXEC_ENCLS_EXITING)

Definition at line 554 of file vmx.h.

KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL

#define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL    (TERTIARY_EXEC_IPI_VIRT)

Definition at line 582 of file vmx.h.

KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS

#define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS

Value:

    (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |              \
     VM_ENTRY_LOAD_IA32_PAT |                   \
     VM_ENTRY_LOAD_IA32_EFER |                  \
     VM_ENTRY_LOAD_BNDCFGS |                    \
     VM_ENTRY_PT_CONCEAL_PIP |                  \
     VM_ENTRY_LOAD_IA32_RTIT_CTL)

Definition at line 481 of file vmx.h.

KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS

#define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS

Value:

          (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |         \
           VM_EXIT_SAVE_IA32_PAT |                  \
           VM_EXIT_LOAD_IA32_PAT |                  \
           VM_EXIT_SAVE_IA32_EFER |                 \
           VM_EXIT_SAVE_VMX_PREEMPTION_TIMER |          \
           VM_EXIT_LOAD_IA32_EFER |                 \
           VM_EXIT_CLEAR_BNDCFGS |                  \
           VM_EXIT_PT_CONCEAL_PIP |                 \
           VM_EXIT_CLEAR_IA32_RTIT_CTL)

Definition at line 500 of file vmx.h.

KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL

#define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL    __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL

Definition at line 538 of file vmx.h.

KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL

#define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL

Value:

    (PIN_BASED_EXT_INTR_MASK |                  \
     PIN_BASED_NMI_EXITING)

Definition at line 511 of file vmx.h.

KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL

#define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL   0

Definition at line 553 of file vmx.h.

KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL

#define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL   0

Definition at line 581 of file vmx.h.

KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS

#define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS    __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS

Definition at line 478 of file vmx.h.

KVM_REQUIRED_VMX_VM_EXIT_CONTROLS

#define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS    __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS

Definition at line 497 of file vmx.h.

MAX_NR_LOADSTORE_MSRS

#define MAX_NR_LOADSTORE_MSRS   8

Definition at line 31 of file vmx.h.

MAX_NR_USER_RETURN_MSRS

#define MAX_NR_USER_RETURN_MSRS   4

Definition at line 28 of file vmx.h.

MAX_POSSIBLE_PASSTHROUGH_MSRS

#define MAX_POSSIBLE_PASSTHROUGH_MSRS   16

Definition at line 362 of file vmx.h.

MSR_TYPE_R

#define MSR_TYPE_R   1

Definition at line 19 of file vmx.h.

MSR_TYPE_RW

#define MSR_TYPE_RW   3

Definition at line 21 of file vmx.h.

MSR_TYPE_W

#define MSR_TYPE_W   2

Definition at line 20 of file vmx.h.

PML_ENTITY_NUM

#define PML_ENTITY_NUM   512

Definition at line 338 of file vmx.h.

RTIT_ADDR_RANGE

#define RTIT_ADDR_RANGE   4

Definition at line 53 of file vmx.h.

VMX_REGS_LAZY_LOAD_SET

#define VMX_REGS_LAZY_LOAD_SET

Value:

                ((1 << VCPU_REGS_RIP) |         \
                (1 << VCPU_REGS_RSP) |          \
                (1 << VCPU_EXREG_RFLAGS) |      \
                (1 << VCPU_EXREG_PDPTR) |       \
                (1 << VCPU_EXREG_SEGMENTS) |    \
                (1 << VCPU_EXREG_CR0) |         \
                (1 << VCPU_EXREG_CR3) |         \
                (1 << VCPU_EXREG_CR4) |         \
                (1 << VCPU_EXREG_EXIT_INFO_1) | \
                (1 << VCPU_EXREG_EXIT_INFO_2))

Definition at line 623 of file vmx.h.

X2APIC_MSR

#define X2APIC_MSR

(

r

)

(APIC_BASE_MSR + ((r) >> 4))

Definition at line 23 of file vmx.h.

Enumeration Type Documentation

segment_cache_field

enum segment_cache_field

Enumerator
SEG_FIELD_SEL
SEG_FIELD_BASE
SEG_FIELD_LIMIT
SEG_FIELD_AR
SEG_FIELD_NR

Definition at line 44 of file vmx.h.

                         {
    SEG_FIELD_SEL = 0,
    SEG_FIELD_BASE = 1,
    SEG_FIELD_LIMIT = 2,
    SEG_FIELD_AR = 3,
 
    SEG_FIELD_NR = 4
};

Function Documentation

__vmx_guest_state_valid()

bool __vmx_guest_state_valid

(

struct kvm_vcpu *

vcpu

)

Definition at line 3796 of file vmx.c.

{
    /* real mode guest state checks */
    if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
        if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
            return false;
        if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
            return false;
        if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
            return false;
        if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
            return false;
        if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
            return false;
        if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
            return false;
    } else {
    /* protected mode guest state checks */
        if (!cs_ss_rpl_check(vcpu))
            return false;
        if (!code_segment_valid(vcpu))
            return false;
        if (!stack_segment_valid(vcpu))
            return false;
        if (!data_segment_valid(vcpu, VCPU_SREG_DS))
            return false;
        if (!data_segment_valid(vcpu, VCPU_SREG_ES))
            return false;
        if (!data_segment_valid(vcpu, VCPU_SREG_FS))
            return false;
        if (!data_segment_valid(vcpu, VCPU_SREG_GS))
            return false;
        if (!tr_valid(vcpu))
            return false;
        if (!ldtr_valid(vcpu))
            return false;
    }
    /* TODO:
     * - Add checks on RIP
     * - Add checks on RFLAGS
     */
 
    return true;
}

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__vmx_set_segment()

void __vmx_set_segment	(	struct kvm_vcpu *	vcpu,
		struct kvm_segment *	var,
		int	seg
	)

Definition at line 3572 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
 
    vmx_segment_cache_clear(vmx);
 
    if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
        vmx->rmode.segs[seg] = *var;
        if (seg == VCPU_SREG_TR)
            vmcs_write16(sf->selector, var->selector);
        else if (var->s)
            fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
        return;
    }
 
    vmcs_writel(sf->base, var->base);
    vmcs_write32(sf->limit, var->limit);
    vmcs_write16(sf->selector, var->selector);
 
    /*
     *   Fix the "Accessed" bit in AR field of segment registers for older
     * qemu binaries.
     *   IA32 arch specifies that at the time of processor reset the
     * "Accessed" bit in the AR field of segment registers is 1. And qemu
     * is setting it to 0 in the userland code. This causes invalid guest
     * state vmexit when "unrestricted guest" mode is turned on.
     *    Fix for this setup issue in cpu_reset is being pushed in the qemu
     * tree. Newer qemu binaries with that qemu fix would not need this
     * kvm hack.
     */
    if (is_unrestricted_guest(vcpu) && (seg != VCPU_SREG_LDTR))
        var->type |= 0x1; /* Accessed */
 
    vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
}

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__vmx_vcpu_run()

bool __vmx_vcpu_run	(	struct vcpu_vmx *	vmx,
		unsigned long *	regs,
		unsigned int	flags
	)

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__vmx_vcpu_run_flags()

unsigned int __vmx_vcpu_run_flags

(

struct vcpu_vmx *

vmx

)

Definition at line 944 of file vmx.c.

{
    unsigned int flags = 0;
 
    if (vmx->loaded_vmcs->launched)
        flags |= VMX_RUN_VMRESUME;
 
    /*
     * If writes to the SPEC_CTRL MSR aren't intercepted, the guest is free
     * to change it directly without causing a vmexit.  In that case read
     * it after vmexit and store it in vmx->spec_ctrl.
     */
    if (!msr_write_intercepted(vmx, MSR_IA32_SPEC_CTRL))
        flags |= VMX_RUN_SAVE_SPEC_CTRL;
 
    return flags;
}

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alloc_loaded_vmcs()

int alloc_loaded_vmcs

(

struct loaded_vmcs *

loaded_vmcs

)

Definition at line 2905 of file vmx.c.

{
    loaded_vmcs->vmcs = alloc_vmcs(false);
    if (!loaded_vmcs->vmcs)
        return -ENOMEM;
 
    vmcs_clear(loaded_vmcs->vmcs);
 
    loaded_vmcs->shadow_vmcs = NULL;
    loaded_vmcs->hv_timer_soft_disabled = false;
    loaded_vmcs->cpu = -1;
    loaded_vmcs->launched = 0;
 
    if (cpu_has_vmx_msr_bitmap()) {
        loaded_vmcs->msr_bitmap = (unsigned long *)
                __get_free_page(GFP_KERNEL_ACCOUNT);
        if (!loaded_vmcs->msr_bitmap)
            goto out_vmcs;
        memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
    }
 
    memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
    memset(&loaded_vmcs->controls_shadow, 0,
        sizeof(struct vmcs_controls_shadow));
 
    return 0;
 
out_vmcs:
    free_loaded_vmcs(loaded_vmcs);
    return -ENOMEM;
}

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alloc_vmcs()

static struct vmcs* alloc_vmcs ( bool  shadow )

inlinestatic

Definition at line 707 of file vmx.h.

{
    return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
                  GFP_KERNEL_ACCOUNT);
}

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alloc_vmcs_cpu()

struct vmcs* alloc_vmcs_cpu	(	bool	shadow,
		int	cpu,
		gfp_t	flags
	)

Definition at line 2862 of file vmx.c.

{
    int node = cpu_to_node(cpu);
    struct page *pages;
    struct vmcs *vmcs;
 
    pages = __alloc_pages_node(node, flags, 0);
    if (!pages)
        return NULL;
    vmcs = page_address(pages);
    memset(vmcs, 0, vmcs_config.size);
 
    /* KVM supports Enlightened VMCS v1 only */
    if (kvm_is_using_evmcs())
        vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
    else
        vmcs->hdr.revision_id = vmcs_config.revision_id;
 
    if (shadow)
        vmcs->hdr.shadow_vmcs = 1;
    return vmcs;
}

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allocate_vpid()

int allocate_vpid

(

void

)

Definition at line 3919 of file vmx.c.

{
    int vpid;
 
    if (!enable_vpid)
        return 0;
    spin_lock(&vmx_vpid_lock);
    vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
    if (vpid < VMX_NR_VPIDS)
        __set_bit(vpid, vmx_vpid_bitmap);
    else
        vpid = 0;
    spin_unlock(&vmx_vpid_lock);
    return vpid;
}

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construct_eptp()

u64 construct_eptp	(	struct kvm_vcpu *	vcpu,
		hpa_t	root_hpa,
		int	root_level
	)

Definition at line 3371 of file vmx.c.

{
    u64 eptp = VMX_EPTP_MT_WB;
 
    eptp |= (root_level == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
 
    if (enable_ept_ad_bits &&
        (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
        eptp |= VMX_EPTP_AD_ENABLE_BIT;
    eptp |= root_hpa;
 
    return eptp;
}

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dump_vmcs()

void dump_vmcs

(

struct kvm_vcpu *

vcpu

)

Definition at line 6232 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    u32 vmentry_ctl, vmexit_ctl;
    u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control;
    u64 tertiary_exec_control;
    unsigned long cr4;
    int efer_slot;
 
    if (!dump_invalid_vmcs) {
        pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
        return;
    }
 
    vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
    vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
    cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
    pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
    cr4 = vmcs_readl(GUEST_CR4);
 
    if (cpu_has_secondary_exec_ctrls())
        secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
    else
        secondary_exec_control = 0;
 
    if (cpu_has_tertiary_exec_ctrls())
        tertiary_exec_control = vmcs_read64(TERTIARY_VM_EXEC_CONTROL);
    else
        tertiary_exec_control = 0;
 
    pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
           vmx->loaded_vmcs->vmcs, vcpu->arch.last_vmentry_cpu);
    pr_err("*** Guest State ***\n");
    pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
           vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
           vmcs_readl(CR0_GUEST_HOST_MASK));
    pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
           cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
    pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
    if (cpu_has_vmx_ept()) {
        pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
               vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
        pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
               vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
    }
    pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
           vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
    pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
           vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
    pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
           vmcs_readl(GUEST_SYSENTER_ESP),
           vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
    vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
    vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
    vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
    vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
    vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
    vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
    vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
    vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
    vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
    vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
    efer_slot = vmx_find_loadstore_msr_slot(&vmx->msr_autoload.guest, MSR_EFER);
    if (vmentry_ctl & VM_ENTRY_LOAD_IA32_EFER)
        pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER));
    else if (efer_slot >= 0)
        pr_err("EFER= 0x%016llx (autoload)\n",
               vmx->msr_autoload.guest.val[efer_slot].value);
    else if (vmentry_ctl & VM_ENTRY_IA32E_MODE)
        pr_err("EFER= 0x%016llx (effective)\n",
               vcpu->arch.efer | (EFER_LMA | EFER_LME));
    else
        pr_err("EFER= 0x%016llx (effective)\n",
               vcpu->arch.efer & ~(EFER_LMA | EFER_LME));
    if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PAT)
        pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT));
    pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
           vmcs_read64(GUEST_IA32_DEBUGCTL),
           vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
    if (cpu_has_load_perf_global_ctrl() &&
        vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
        pr_err("PerfGlobCtl = 0x%016llx\n",
               vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
    if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
        pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
    pr_err("Interruptibility = %08x  ActivityState = %08x\n",
           vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
           vmcs_read32(GUEST_ACTIVITY_STATE));
    if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
        pr_err("InterruptStatus = %04x\n",
               vmcs_read16(GUEST_INTR_STATUS));
    if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT) > 0)
        vmx_dump_msrs("guest autoload", &vmx->msr_autoload.guest);
    if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT) > 0)
        vmx_dump_msrs("guest autostore", &vmx->msr_autostore.guest);
 
    pr_err("*** Host State ***\n");
    pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
           vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
    pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
           vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
           vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
           vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
           vmcs_read16(HOST_TR_SELECTOR));
    pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
           vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
           vmcs_readl(HOST_TR_BASE));
    pr_err("GDTBase=%016lx IDTBase=%016lx\n",
           vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
    pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
           vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
           vmcs_readl(HOST_CR4));
    pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
           vmcs_readl(HOST_IA32_SYSENTER_ESP),
           vmcs_read32(HOST_IA32_SYSENTER_CS),
           vmcs_readl(HOST_IA32_SYSENTER_EIP));
    if (vmexit_ctl & VM_EXIT_LOAD_IA32_EFER)
        pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER));
    if (vmexit_ctl & VM_EXIT_LOAD_IA32_PAT)
        pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT));
    if (cpu_has_load_perf_global_ctrl() &&
        vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
        pr_err("PerfGlobCtl = 0x%016llx\n",
               vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
    if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT) > 0)
        vmx_dump_msrs("host autoload", &vmx->msr_autoload.host);
 
    pr_err("*** Control State ***\n");
    pr_err("CPUBased=0x%08x SecondaryExec=0x%08x TertiaryExec=0x%016llx\n",
           cpu_based_exec_ctrl, secondary_exec_control, tertiary_exec_control);
    pr_err("PinBased=0x%08x EntryControls=%08x ExitControls=%08x\n",
           pin_based_exec_ctrl, vmentry_ctl, vmexit_ctl);
    pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
           vmcs_read32(EXCEPTION_BITMAP),
           vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
           vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
    pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
           vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
           vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
           vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
    pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
           vmcs_read32(VM_EXIT_INTR_INFO),
           vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
           vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
    pr_err("        reason=%08x qualification=%016lx\n",
           vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
    pr_err("IDTVectoring: info=%08x errcode=%08x\n",
           vmcs_read32(IDT_VECTORING_INFO_FIELD),
           vmcs_read32(IDT_VECTORING_ERROR_CODE));
    pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
    if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
        pr_err("TSC Multiplier = 0x%016llx\n",
               vmcs_read64(TSC_MULTIPLIER));
    if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) {
        if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
            u16 status = vmcs_read16(GUEST_INTR_STATUS);
            pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff);
        }
        pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
        if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
            pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR));
        pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR));
    }
    if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
        pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
    if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
        pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
    if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
        pr_err("PLE Gap=%08x Window=%08x\n",
               vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
    if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
        pr_err("Virtual processor ID = 0x%04x\n",
               vmcs_read16(VIRTUAL_PROCESSOR_ID));
}

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ept_save_pdptrs()

void ept_save_pdptrs

(

struct kvm_vcpu *

vcpu

)

Definition at line 3246 of file vmx.c.

{
    struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
 
    if (WARN_ON_ONCE(!is_pae_paging(vcpu)))
        return;
 
    mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
    mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
    mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
    mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
 
    kvm_register_mark_available(vcpu, VCPU_EXREG_PDPTR);
}

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free_loaded_vmcs()

void free_loaded_vmcs

(

struct loaded_vmcs *

loaded_vmcs

)

Definition at line 2893 of file vmx.c.

{
    if (!loaded_vmcs->vmcs)
        return;
    loaded_vmcs_clear(loaded_vmcs);
    free_vmcs(loaded_vmcs->vmcs);
    loaded_vmcs->vmcs = NULL;
    if (loaded_vmcs->msr_bitmap)
        free_page((unsigned long)loaded_vmcs->msr_bitmap);
    WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
}

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free_vmcs()

void free_vmcs

(

struct vmcs *

vmcs

)

Definition at line 2885 of file vmx.c.

{
    free_page((unsigned long)vmcs);
}

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free_vpid()

void free_vpid

(

int

vpid

)

Definition at line 3935 of file vmx.c.

{
    if (!enable_vpid || vpid == 0)
        return;
    spin_lock(&vmx_vpid_lock);
    __clear_bit(vpid, vmx_vpid_bitmap);
    spin_unlock(&vmx_vpid_lock);
}

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intel_pmu_create_guest_lbr_event()

int intel_pmu_create_guest_lbr_event

(

struct kvm_vcpu *

vcpu

)

Definition at line 254 of file pmu_intel.c.

{
    struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
    struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
    struct perf_event *event;
 
    /*
     * The perf_event_attr is constructed in the minimum efficient way:
     * - set 'pinned = true' to make it task pinned so that if another
     *   cpu pinned event reclaims LBR, the event->oncpu will be set to -1;
     * - set '.exclude_host = true' to record guest branches behavior;
     *
     * - set '.config = INTEL_FIXED_VLBR_EVENT' to indicates host perf
     *   schedule the event without a real HW counter but a fake one;
     *   check is_guest_lbr_event() and __intel_get_event_constraints();
     *
     * - set 'sample_type = PERF_SAMPLE_BRANCH_STACK' and
     *   'branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK |
     *   PERF_SAMPLE_BRANCH_USER' to configure it as a LBR callstack
     *   event, which helps KVM to save/restore guest LBR records
     *   during host context switches and reduces quite a lot overhead,
     *   check branch_user_callstack() and intel_pmu_lbr_sched_task();
     */
    struct perf_event_attr attr = {
        .type = PERF_TYPE_RAW,
        .size = sizeof(attr),
        .config = INTEL_FIXED_VLBR_EVENT,
        .sample_type = PERF_SAMPLE_BRANCH_STACK,
        .pinned = true,
        .exclude_host = true,
        .branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK |
                    PERF_SAMPLE_BRANCH_USER,
    };
 
    if (unlikely(lbr_desc->event)) {
        __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
        return 0;
    }
 
    event = perf_event_create_kernel_counter(&attr, -1,
                        current, NULL, NULL);
    if (IS_ERR(event)) {
        pr_debug_ratelimited("%s: failed %ld\n",
                    __func__, PTR_ERR(event));
        return PTR_ERR(event);
    }
    lbr_desc->event = event;
    pmu->event_count++;
    __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
    return 0;
}

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intel_pmu_cross_mapped_check()

void intel_pmu_cross_mapped_check

(

struct kvm_pmu *

pmu

)

Definition at line 746 of file pmu_intel.c.

{
    struct kvm_pmc *pmc = NULL;
    int bit, hw_idx;
 
    for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl,
             X86_PMC_IDX_MAX) {
        pmc = intel_pmc_idx_to_pmc(pmu, bit);
 
        if (!pmc || !pmc_speculative_in_use(pmc) ||
            !pmc_is_globally_enabled(pmc) || !pmc->perf_event)
            continue;
 
        /*
         * A negative index indicates the event isn't mapped to a
         * physical counter in the host, e.g. due to contention.
         */
        hw_idx = pmc->perf_event->hw.idx;
        if (hw_idx != pmc->idx && hw_idx > -1)
            pmu->host_cross_mapped_mask |= BIT_ULL(hw_idx);
    }
}

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intel_pmu_lbr_is_enabled()

static bool intel_pmu_lbr_is_enabled ( struct kvm_vcpu *  vcpu )

inlinestatic

Definition at line 672 of file vmx.h.

{
    return !!vcpu_to_lbr_records(vcpu)->nr;
}

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is_unrestricted_guest()

static bool is_unrestricted_guest ( struct kvm_vcpu *  vcpu )

inlinestatic

Definition at line 727 of file vmx.h.

{
    return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
        (secondary_exec_controls_get(to_vmx(vcpu)) &
        SECONDARY_EXEC_UNRESTRICTED_GUEST));
}

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loaded_vmcs_clear()

void loaded_vmcs_clear

(

struct loaded_vmcs *

loaded_vmcs

)

Definition at line 814 of file vmx.c.

{
    int cpu = loaded_vmcs->cpu;
 
    if (cpu != -1)
        smp_call_function_single(cpu,
             __loaded_vmcs_clear, loaded_vmcs, 1);
}

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pt_update_intercept_for_msr()

void pt_update_intercept_for_msr

(

struct kvm_vcpu *

vcpu

)

Definition at line 4098 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN);
    u32 i;
 
    vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_STATUS, MSR_TYPE_RW, flag);
    vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_BASE, MSR_TYPE_RW, flag);
    vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_OUTPUT_MASK, MSR_TYPE_RW, flag);
    vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_CR3_MATCH, MSR_TYPE_RW, flag);
    for (i = 0; i < vmx->pt_desc.num_address_ranges; i++) {
        vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag);
        vmx_set_intercept_for_msr(vcpu, MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag);
    }
}

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set_cr4_guest_host_mask()

void set_cr4_guest_host_mask

(

struct vcpu_vmx *

vmx

)

Definition at line 4363 of file vmx.c.

{
    struct kvm_vcpu *vcpu = &vmx->vcpu;
 
    vcpu->arch.cr4_guest_owned_bits = KVM_POSSIBLE_CR4_GUEST_BITS &
                      ~vcpu->arch.cr4_guest_rsvd_bits;
    if (!enable_ept) {
        vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_TLBFLUSH_BITS;
        vcpu->arch.cr4_guest_owned_bits &= ~X86_CR4_PDPTR_BITS;
    }
    if (is_guest_mode(&vmx->vcpu))
        vcpu->arch.cr4_guest_owned_bits &=
            ~get_vmcs12(vcpu)->cr4_guest_host_mask;
    vmcs_writel(CR4_GUEST_HOST_MASK, ~vcpu->arch.cr4_guest_owned_bits);
}

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to_kvm_vmx()

static __always_inline struct kvm_vmx* to_kvm_vmx ( struct kvm *  kvm )

static

Definition at line 652 of file vmx.h.

{
    return container_of(kvm, struct kvm_vmx, kvm);
}

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to_vmx()

static __always_inline struct vcpu_vmx* to_vmx ( struct kvm_vcpu *  vcpu )

static

Definition at line 657 of file vmx.h.

{
    return container_of(vcpu, struct vcpu_vmx, vcpu);
}

vcpu_to_lbr_desc()

static struct lbr_desc* vcpu_to_lbr_desc ( struct kvm_vcpu *  vcpu )

inlinestatic

Definition at line 662 of file vmx.h.

{
    return &to_vmx(vcpu)->lbr_desc;
}

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vcpu_to_lbr_records()

static struct x86_pmu_lbr* vcpu_to_lbr_records ( struct kvm_vcpu *  vcpu )

inlinestatic

Definition at line 667 of file vmx.h.

{
    return &vcpu_to_lbr_desc(vcpu)->records;
}

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vmx_can_use_ipiv()

static bool vmx_can_use_ipiv ( struct kvm_vcpu *  vcpu )

inlinestatic

Definition at line 747 of file vmx.h.

{
    return  lapic_in_kernel(vcpu) && enable_ipiv;
}

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vmx_disable_intercept_for_msr()

void vmx_disable_intercept_for_msr	(	struct kvm_vcpu *	vcpu,
		u32	msr,
		int	type
	)

Definition at line 3962 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
 
    if (!cpu_has_vmx_msr_bitmap())
        return;
 
    vmx_msr_bitmap_l01_changed(vmx);
 
    /*
     * Mark the desired intercept state in shadow bitmap, this is needed
     * for resync when the MSR filters change.
    */
    if (is_valid_passthrough_msr(msr)) {
        int idx = possible_passthrough_msr_slot(msr);
 
        if (idx != -ENOENT) {
            if (type & MSR_TYPE_R)
                clear_bit(idx, vmx->shadow_msr_intercept.read);
            if (type & MSR_TYPE_W)
                clear_bit(idx, vmx->shadow_msr_intercept.write);
        }
    }
 
    if ((type & MSR_TYPE_R) &&
        !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ)) {
        vmx_set_msr_bitmap_read(msr_bitmap, msr);
        type &= ~MSR_TYPE_R;
    }
 
    if ((type & MSR_TYPE_W) &&
        !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE)) {
        vmx_set_msr_bitmap_write(msr_bitmap, msr);
        type &= ~MSR_TYPE_W;
    }
 
    if (type & MSR_TYPE_R)
        vmx_clear_msr_bitmap_read(msr_bitmap, msr);
 
    if (type & MSR_TYPE_W)
        vmx_clear_msr_bitmap_write(msr_bitmap, msr);
}

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vmx_emulation_required()

bool vmx_emulation_required

(

struct kvm_vcpu *

vcpu

)

Definition at line 1504 of file vmx.c.

{
    return emulate_invalid_guest_state && !vmx_guest_state_valid(vcpu);
}

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vmx_enable_intercept_for_msr()

void vmx_enable_intercept_for_msr	(	struct kvm_vcpu *	vcpu,
		u32	msr,
		int	type
	)

Definition at line 4006 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
 
    if (!cpu_has_vmx_msr_bitmap())
        return;
 
    vmx_msr_bitmap_l01_changed(vmx);
 
    /*
     * Mark the desired intercept state in shadow bitmap, this is needed
     * for resync when the MSR filter changes.
    */
    if (is_valid_passthrough_msr(msr)) {
        int idx = possible_passthrough_msr_slot(msr);
 
        if (idx != -ENOENT) {
            if (type & MSR_TYPE_R)
                set_bit(idx, vmx->shadow_msr_intercept.read);
            if (type & MSR_TYPE_W)
                set_bit(idx, vmx->shadow_msr_intercept.write);
        }
    }
 
    if (type & MSR_TYPE_R)
        vmx_set_msr_bitmap_read(msr_bitmap, msr);
 
    if (type & MSR_TYPE_W)
        vmx_set_msr_bitmap_write(msr_bitmap, msr);
}

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vmx_ept_load_pdptrs()

void vmx_ept_load_pdptrs

(

struct kvm_vcpu *

vcpu

)

Definition at line 3231 of file vmx.c.

{
    struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
 
    if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR))
        return;
 
    if (is_pae_paging(vcpu)) {
        vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
        vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
        vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
        vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
    }
}

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vmx_find_loadstore_msr_slot()

int vmx_find_loadstore_msr_slot	(	struct vmx_msrs *	m,
		u32	msr
	)

Definition at line 969 of file vmx.c.

{
    unsigned int i;
 
    for (i = 0; i < m->nr; ++i) {
        if (m->val[i].index == msr)
            return i;
    }
    return -ENOENT;
}

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vmx_find_uret_msr()

struct vmx_uret_msr* vmx_find_uret_msr	(	struct vcpu_vmx *	vmx,
		u32	msr
	)

Definition at line 713 of file vmx.c.

{
    int i;
 
    i = kvm_find_user_return_msr(msr);
    if (i >= 0)
        return &vmx->guest_uret_msrs[i];
    return NULL;
}

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vmx_get_cpl()

int vmx_get_cpl

(

struct kvm_vcpu *

vcpu

)

Definition at line 3543 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
 
    if (unlikely(vmx->rmode.vm86_active))
        return 0;
    else {
        int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
        return VMX_AR_DPL(ar);
    }
}

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vmx_get_exit_qual()

static __always_inline unsigned long vmx_get_exit_qual ( struct kvm_vcpu *  vcpu )

static

Definition at line 681 of file vmx.h.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
 
    if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1))
        vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
 
    return vmx->exit_qualification;
}

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vmx_get_instr_info_reg2()

static int vmx_get_instr_info_reg2 ( u32  vmx_instr_info )

inlinestatic

Definition at line 742 of file vmx.h.

{
    return (vmx_instr_info >> 28) & 0xf;
}

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vmx_get_interrupt_shadow()

u32 vmx_get_interrupt_shadow

(

struct kvm_vcpu *

vcpu

)

Definition at line 1561 of file vmx.c.

{
    u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
    int ret = 0;
 
    if (interruptibility & GUEST_INTR_STATE_STI)
        ret |= KVM_X86_SHADOW_INT_STI;
    if (interruptibility & GUEST_INTR_STATE_MOV_SS)
        ret |= KVM_X86_SHADOW_INT_MOV_SS;
 
    return ret;
}

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vmx_get_intr_info()

static __always_inline u32 vmx_get_intr_info ( struct kvm_vcpu *  vcpu )

static

Definition at line 691 of file vmx.h.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
 
    if (!kvm_register_test_and_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2))
        vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
 
    return vmx->exit_intr_info;
}

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vmx_get_l2_tsc_multiplier()

u64 vmx_get_l2_tsc_multiplier

(

struct kvm_vcpu *

vcpu

)

Definition at line 1907 of file vmx.c.

{
    struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 
    if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING) &&
        nested_cpu_has2(vmcs12, SECONDARY_EXEC_TSC_SCALING))
        return vmcs12->tsc_multiplier;
 
    return kvm_caps.default_tsc_scaling_ratio;
}

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vmx_get_l2_tsc_offset()

u64 vmx_get_l2_tsc_offset

(

struct kvm_vcpu *

vcpu

)

Definition at line 1897 of file vmx.c.

{
    struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 
    if (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETTING))
        return vmcs12->tsc_offset;
 
    return 0;
}

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vmx_get_nmi_mask()

bool vmx_get_nmi_mask

(

struct kvm_vcpu *

vcpu

)

Definition at line 4991 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    bool masked;
 
    if (!enable_vnmi)
        return vmx->loaded_vmcs->soft_vnmi_blocked;
    if (vmx->loaded_vmcs->nmi_known_unmasked)
        return false;
    masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
    vmx->loaded_vmcs->nmi_known_unmasked = !masked;
    return masked;
}

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vmx_get_rflags()

unsigned long vmx_get_rflags

(

struct kvm_vcpu *

vcpu

)

Definition at line 1509 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    unsigned long rflags, save_rflags;
 
    if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) {
        kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
        rflags = vmcs_readl(GUEST_RFLAGS);
        if (vmx->rmode.vm86_active) {
            rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
            save_rflags = vmx->rmode.save_rflags;
            rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
        }
        vmx->rflags = rflags;
    }
    return vmx->rflags;
}

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vmx_get_rvi()

static u8 vmx_get_rvi ( void  )

inlinestatic

Definition at line 466 of file vmx.h.

{
    return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
}

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vmx_get_segment()

void vmx_get_segment	(	struct kvm_vcpu *	vcpu,
		struct kvm_segment *	var,
		int	seg
	)

Definition at line 3496 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    u32 ar;
 
    if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
        *var = vmx->rmode.segs[seg];
        if (seg == VCPU_SREG_TR
            || var->selector == vmx_read_guest_seg_selector(vmx, seg))
            return;
        var->base = vmx_read_guest_seg_base(vmx, seg);
        var->selector = vmx_read_guest_seg_selector(vmx, seg);
        return;
    }
    var->base = vmx_read_guest_seg_base(vmx, seg);
    var->limit = vmx_read_guest_seg_limit(vmx, seg);
    var->selector = vmx_read_guest_seg_selector(vmx, seg);
    ar = vmx_read_guest_seg_ar(vmx, seg);
    var->unusable = (ar >> 16) & 1;
    var->type = ar & 15;
    var->s = (ar >> 4) & 1;
    var->dpl = (ar >> 5) & 3;
    /*
     * Some userspaces do not preserve unusable property. Since usable
     * segment has to be present according to VMX spec we can use present
     * property to amend userspace bug by making unusable segment always
     * nonpresent. vmx_segment_access_rights() already marks nonpresent
     * segment as unusable.
     */
    var->present = !var->unusable;
    var->avl = (ar >> 12) & 1;
    var->l = (ar >> 13) & 1;
    var->db = (ar >> 14) & 1;
    var->g = (ar >> 15) & 1;
}

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vmx_get_untagged_addr()

gva_t vmx_get_untagged_addr	(	struct kvm_vcpu *	vcpu,
		gva_t	gva,
		unsigned int	flags
	)

Definition at line 8250 of file vmx.c.

{
    int lam_bit;
    unsigned long cr3_bits;
 
    if (flags & (X86EMUL_F_FETCH | X86EMUL_F_IMPLICIT | X86EMUL_F_INVLPG))
        return gva;
 
    if (!is_64_bit_mode(vcpu))
        return gva;
 
    /*
     * Bit 63 determines if the address should be treated as user address
     * or a supervisor address.
     */
    if (!(gva & BIT_ULL(63))) {
        cr3_bits = kvm_get_active_cr3_lam_bits(vcpu);
        if (!(cr3_bits & (X86_CR3_LAM_U57 | X86_CR3_LAM_U48)))
            return gva;
 
        /* LAM_U48 is ignored if LAM_U57 is set. */
        lam_bit = cr3_bits & X86_CR3_LAM_U57 ? 56 : 47;
    } else {
        if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_LAM_SUP))
            return gva;
 
        lam_bit = kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 56 : 47;
    }
 
    /*
     * Untag the address by sign-extending the lam_bit, but NOT to bit 63.
     * Bit 63 is retained from the raw virtual address so that untagging
     * doesn't change a user access to a supervisor access, and vice versa.
     */
    return (sign_extend64(gva, lam_bit) & ~BIT_ULL(63)) | (gva & BIT_ULL(63));
}

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vmx_guest_inject_ac()

bool vmx_guest_inject_ac

(

struct kvm_vcpu *

vcpu

)

Definition at line 5174 of file vmx.c.

{
    if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
        return true;
 
    return vmx_get_cpl(vcpu) == 3 && kvm_is_cr0_bit_set(vcpu, X86_CR0_AM) &&
           (kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
}

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vmx_guest_state_valid()

static bool vmx_guest_state_valid ( struct kvm_vcpu *  vcpu )

inlinestatic

Definition at line 735 of file vmx.h.

{
    return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
}

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vmx_has_waitpkg()

static bool vmx_has_waitpkg ( struct vcpu_vmx *  vmx )

inlinestatic

Definition at line 713 of file vmx.h.

{
    return secondary_exec_controls_get(vmx) &
        SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
}

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vmx_interrupt_blocked()

bool vmx_interrupt_blocked

(

struct kvm_vcpu *

vcpu

)

Definition at line 5050 of file vmx.c.

{
    if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
        return false;
 
    return !(vmx_get_rflags(vcpu) & X86_EFLAGS_IF) ||
           (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
        (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
}

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vmx_l1_guest_owned_cr0_bits()

static unsigned long vmx_l1_guest_owned_cr0_bits ( void  )

inlinestatic

Definition at line 634 of file vmx.h.

{
    unsigned long bits = KVM_POSSIBLE_CR0_GUEST_BITS;
 
    /*
     * CR0.WP needs to be intercepted when KVM is shadowing legacy paging
     * in order to construct shadow PTEs with the correct protections.
     * Note!  CR0.WP technically can be passed through to the guest if
     * paging is disabled, but checking CR0.PG would generate a cyclical
     * dependency of sorts due to forcing the caller to ensure CR0 holds
     * the correct value prior to determining which CR0 bits can be owned
     * by L1.  Keep it simple and limit the optimization to EPT.
     */
    if (!enable_ept)
        bits &= ~X86_CR0_WP;
    return bits;
}

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vmx_need_pf_intercept()

static bool vmx_need_pf_intercept ( struct kvm_vcpu *  vcpu )

inlinestatic

Definition at line 719 of file vmx.h.

{
    if (!enable_ept)
        return true;
 
    return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
}

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vmx_nmi_blocked()

bool vmx_nmi_blocked

(

struct kvm_vcpu *

vcpu

)

Definition at line 5025 of file vmx.c.

{
    if (is_guest_mode(vcpu) && nested_exit_on_nmi(vcpu))
        return false;
 
    if (!enable_vnmi && to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
        return true;
 
    return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
        (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
         GUEST_INTR_STATE_NMI));
}

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vmx_passthrough_lbr_msrs()

void vmx_passthrough_lbr_msrs

(

struct kvm_vcpu *

vcpu

)

Definition at line 713 of file pmu_intel.c.

{
    struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
    struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
 
    if (!lbr_desc->event) {
        vmx_disable_lbr_msrs_passthrough(vcpu);
        if (vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR)
            goto warn;
        if (test_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use))
            goto warn;
        return;
    }
 
    if (lbr_desc->event->state < PERF_EVENT_STATE_ACTIVE) {
        vmx_disable_lbr_msrs_passthrough(vcpu);
        __clear_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
        goto warn;
    } else
        vmx_enable_lbr_msrs_passthrough(vcpu);
 
    return;
 
warn:
    pr_warn_ratelimited("vcpu-%d: fail to passthrough LBR.\n", vcpu->vcpu_id);
}

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vmx_prepare_switch_to_guest()

void vmx_prepare_switch_to_guest

(

struct kvm_vcpu *

vcpu

)

Definition at line 1282 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    struct vmcs_host_state *host_state;
#ifdef CONFIG_X86_64
    int cpu = raw_smp_processor_id();
#endif
    unsigned long fs_base, gs_base;
    u16 fs_sel, gs_sel;
    int i;
 
    vmx->req_immediate_exit = false;
 
    /*
     * Note that guest MSRs to be saved/restored can also be changed
     * when guest state is loaded. This happens when guest transitions
     * to/from long-mode by setting MSR_EFER.LMA.
     */
    if (!vmx->guest_uret_msrs_loaded) {
        vmx->guest_uret_msrs_loaded = true;
        for (i = 0; i < kvm_nr_uret_msrs; ++i) {
            if (!vmx->guest_uret_msrs[i].load_into_hardware)
                continue;
 
            kvm_set_user_return_msr(i,
                        vmx->guest_uret_msrs[i].data,
                        vmx->guest_uret_msrs[i].mask);
        }
    }
 
    if (vmx->nested.need_vmcs12_to_shadow_sync)
        nested_sync_vmcs12_to_shadow(vcpu);
 
    if (vmx->guest_state_loaded)
        return;
 
    host_state = &vmx->loaded_vmcs->host_state;
 
    /*
     * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
     * allow segment selectors with cpl > 0 or ti == 1.
     */
    host_state->ldt_sel = kvm_read_ldt();
 
#ifdef CONFIG_X86_64
    savesegment(ds, host_state->ds_sel);
    savesegment(es, host_state->es_sel);
 
    gs_base = cpu_kernelmode_gs_base(cpu);
    if (likely(is_64bit_mm(current->mm))) {
        current_save_fsgs();
        fs_sel = current->thread.fsindex;
        gs_sel = current->thread.gsindex;
        fs_base = current->thread.fsbase;
        vmx->msr_host_kernel_gs_base = current->thread.gsbase;
    } else {
        savesegment(fs, fs_sel);
        savesegment(gs, gs_sel);
        fs_base = read_msr(MSR_FS_BASE);
        vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
    }
 
    wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
#else
    savesegment(fs, fs_sel);
    savesegment(gs, gs_sel);
    fs_base = segment_base(fs_sel);
    gs_base = segment_base(gs_sel);
#endif
 
    vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base);
    vmx->guest_state_loaded = true;
}

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vmx_set_constant_host_state()

void vmx_set_constant_host_state

(

struct vcpu_vmx *

vmx

)

Definition at line 4296 of file vmx.c.

{
    u32 low32, high32;
    unsigned long tmpl;
    unsigned long cr0, cr3, cr4;
 
    cr0 = read_cr0();
    WARN_ON(cr0 & X86_CR0_TS);
    vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
 
    /*
     * Save the most likely value for this task's CR3 in the VMCS.
     * We can't use __get_current_cr3_fast() because we're not atomic.
     */
    cr3 = __read_cr3();
    vmcs_writel(HOST_CR3, cr3);     /* 22.2.3  FIXME: shadow tables */
    vmx->loaded_vmcs->host_state.cr3 = cr3;
 
    /* Save the most likely value for this task's CR4 in the VMCS. */
    cr4 = cr4_read_shadow();
    vmcs_writel(HOST_CR4, cr4);         /* 22.2.3, 22.2.5 */
    vmx->loaded_vmcs->host_state.cr4 = cr4;
 
    vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
#ifdef CONFIG_X86_64
    /*
     * Load null selectors, so we can avoid reloading them in
     * vmx_prepare_switch_to_host(), in case userspace uses
     * the null selectors too (the expected case).
     */
    vmcs_write16(HOST_DS_SELECTOR, 0);
    vmcs_write16(HOST_ES_SELECTOR, 0);
#else
    vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
    vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
#endif
    vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
    vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
 
    vmcs_writel(HOST_IDTR_BASE, host_idt_base);   /* 22.2.4 */
 
    vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */
 
    rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
    vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
 
    /*
     * SYSENTER is used for 32-bit system calls on either 32-bit or
     * 64-bit kernels.  It is always zero If neither is allowed, otherwise
     * vmx_vcpu_load_vmcs loads it with the per-CPU entry stack (and may
     * have already done so!).
     */
    if (!IS_ENABLED(CONFIG_IA32_EMULATION) && !IS_ENABLED(CONFIG_X86_32))
        vmcs_writel(HOST_IA32_SYSENTER_ESP, 0);
 
    rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
    vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
 
    if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
        rdmsr(MSR_IA32_CR_PAT, low32, high32);
        vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
    }
 
    if (cpu_has_load_ia32_efer())
        vmcs_write64(HOST_IA32_EFER, host_efer);
}

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vmx_set_cr0()

void vmx_set_cr0	(	struct kvm_vcpu *	vcpu,
		unsigned long	cr0
	)

Definition at line 3275 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    unsigned long hw_cr0, old_cr0_pg;
    u32 tmp;
 
    old_cr0_pg = kvm_read_cr0_bits(vcpu, X86_CR0_PG);
 
    hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
    if (enable_unrestricted_guest)
        hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
    else {
        hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
        if (!enable_ept)
            hw_cr0 |= X86_CR0_WP;
 
        if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
            enter_pmode(vcpu);
 
        if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
            enter_rmode(vcpu);
    }
 
    vmcs_writel(CR0_READ_SHADOW, cr0);
    vmcs_writel(GUEST_CR0, hw_cr0);
    vcpu->arch.cr0 = cr0;
    kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
 
#ifdef CONFIG_X86_64
    if (vcpu->arch.efer & EFER_LME) {
        if (!old_cr0_pg && (cr0 & X86_CR0_PG))
            enter_lmode(vcpu);
        else if (old_cr0_pg && !(cr0 & X86_CR0_PG))
            exit_lmode(vcpu);
    }
#endif
 
    if (enable_ept && !enable_unrestricted_guest) {
        /*
         * Ensure KVM has an up-to-date snapshot of the guest's CR3.  If
         * the below code _enables_ CR3 exiting, vmx_cache_reg() will
         * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
         * KVM's CR3 is installed.
         */
        if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
            vmx_cache_reg(vcpu, VCPU_EXREG_CR3);
 
        /*
         * When running with EPT but not unrestricted guest, KVM must
         * intercept CR3 accesses when paging is _disabled_.  This is
         * necessary because restricted guests can't actually run with
         * paging disabled, and so KVM stuffs its own CR3 in order to
         * run the guest when identity mapped page tables.
         *
         * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
         * update, it may be stale with respect to CR3 interception,
         * e.g. after nested VM-Enter.
         *
         * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
         * stores to forward them to L1, even if KVM does not need to
         * intercept them to preserve its identity mapped page tables.
         */
        if (!(cr0 & X86_CR0_PG)) {
            exec_controls_setbit(vmx, CR3_EXITING_BITS);
        } else if (!is_guest_mode(vcpu)) {
            exec_controls_clearbit(vmx, CR3_EXITING_BITS);
        } else {
            tmp = exec_controls_get(vmx);
            tmp &= ~CR3_EXITING_BITS;
            tmp |= get_vmcs12(vcpu)->cpu_based_vm_exec_control & CR3_EXITING_BITS;
            exec_controls_set(vmx, tmp);
        }
 
        /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
        if ((old_cr0_pg ^ cr0) & X86_CR0_PG)
            vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
 
        /*
         * When !CR0_PG -> CR0_PG, vcpu->arch.cr3 becomes active, but
         * GUEST_CR3 is still vmx->ept_identity_map_addr if EPT + !URG.
         */
        if (!(old_cr0_pg & X86_CR0_PG) && (cr0 & X86_CR0_PG))
            kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
    }
 
    /* depends on vcpu->arch.cr0 to be set to a new value */
    vmx->emulation_required = vmx_emulation_required(vcpu);
}

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vmx_set_cr4()

void vmx_set_cr4	(	struct kvm_vcpu *	vcpu,
		unsigned long	cr4
	)

Definition at line 3432 of file vmx.c.

{
    unsigned long old_cr4 = kvm_read_cr4(vcpu);
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    unsigned long hw_cr4;
 
    /*
     * Pass through host's Machine Check Enable value to hw_cr4, which
     * is in force while we are in guest mode.  Do not let guests control
     * this bit, even if host CR4.MCE == 0.
     */
    hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
    if (enable_unrestricted_guest)
        hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
    else if (vmx->rmode.vm86_active)
        hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
    else
        hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
 
    if (vmx_umip_emulated()) {
        if (cr4 & X86_CR4_UMIP) {
            secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
            hw_cr4 &= ~X86_CR4_UMIP;
        } else if (!is_guest_mode(vcpu) ||
            !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) {
            secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC);
        }
    }
 
    vcpu->arch.cr4 = cr4;
    kvm_register_mark_available(vcpu, VCPU_EXREG_CR4);
 
    if (!enable_unrestricted_guest) {
        if (enable_ept) {
            if (!is_paging(vcpu)) {
                hw_cr4 &= ~X86_CR4_PAE;
                hw_cr4 |= X86_CR4_PSE;
            } else if (!(cr4 & X86_CR4_PAE)) {
                hw_cr4 &= ~X86_CR4_PAE;
            }
        }
 
        /*
         * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
         * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
         * to be manually disabled when guest switches to non-paging
         * mode.
         *
         * If !enable_unrestricted_guest, the CPU is always running
         * with CR0.PG=1 and CR4 needs to be modified.
         * If enable_unrestricted_guest, the CPU automatically
         * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
         */
        if (!is_paging(vcpu))
            hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
    }
 
    vmcs_writel(CR4_READ_SHADOW, cr4);
    vmcs_writel(GUEST_CR4, hw_cr4);
 
    if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
        kvm_update_cpuid_runtime(vcpu);
}

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vmx_set_efer()

int vmx_set_efer	(	struct kvm_vcpu *	vcpu,
		u64	efer
	)

Definition at line 3115 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
 
    /* Nothing to do if hardware doesn't support EFER. */
    if (!vmx_find_uret_msr(vmx, MSR_EFER))
        return 0;
 
    vcpu->arch.efer = efer;
#ifdef CONFIG_X86_64
    if (efer & EFER_LMA)
        vm_entry_controls_setbit(vmx, VM_ENTRY_IA32E_MODE);
    else
        vm_entry_controls_clearbit(vmx, VM_ENTRY_IA32E_MODE);
#else
    if (KVM_BUG_ON(efer & EFER_LMA, vcpu->kvm))
        return 1;
#endif
 
    vmx_setup_uret_msrs(vmx);
    return 0;
}

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vmx_set_host_fs_gs()

void vmx_set_host_fs_gs	(	struct vmcs_host_state *	host,
		u16	fs_sel,
		u16	gs_sel,
		unsigned long	fs_base,
		unsigned long	gs_base
	)

Definition at line 1255 of file vmx.c.

{
    if (unlikely(fs_sel != host->fs_sel)) {
        if (!(fs_sel & 7))
            vmcs_write16(HOST_FS_SELECTOR, fs_sel);
        else
            vmcs_write16(HOST_FS_SELECTOR, 0);
        host->fs_sel = fs_sel;
    }
    if (unlikely(gs_sel != host->gs_sel)) {
        if (!(gs_sel & 7))
            vmcs_write16(HOST_GS_SELECTOR, gs_sel);
        else
            vmcs_write16(HOST_GS_SELECTOR, 0);
        host->gs_sel = gs_sel;
    }
    if (unlikely(fs_base != host->fs_base)) {
        vmcs_writel(HOST_FS_BASE, fs_base);
        host->fs_base = fs_base;
    }
    if (unlikely(gs_base != host->gs_base)) {
        vmcs_writel(HOST_GS_BASE, gs_base);
        host->gs_base = gs_base;
    }
}

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vmx_set_intercept_for_msr()

static void vmx_set_intercept_for_msr ( struct kvm_vcpu *  vcpu, u32  msr, int  type, bool  value  )

inlinestatic

Definition at line 427 of file vmx.h.

{
    if (value)
        vmx_enable_intercept_for_msr(vcpu, msr, type);
    else
        vmx_disable_intercept_for_msr(vcpu, msr, type);
}

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vmx_set_interrupt_shadow()

void vmx_set_interrupt_shadow	(	struct kvm_vcpu *	vcpu,
		int	mask
	)

Definition at line 1574 of file vmx.c.

{
    u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
    u32 interruptibility = interruptibility_old;
 
    interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 
    if (mask & KVM_X86_SHADOW_INT_MOV_SS)
        interruptibility |= GUEST_INTR_STATE_MOV_SS;
    else if (mask & KVM_X86_SHADOW_INT_STI)
        interruptibility |= GUEST_INTR_STATE_STI;
 
    if ((interruptibility != interruptibility_old))
        vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
}

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vmx_set_nmi_mask()

void vmx_set_nmi_mask	(	struct kvm_vcpu *	vcpu,
		bool	masked
	)

Definition at line 5005 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
 
    if (!enable_vnmi) {
        if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
            vmx->loaded_vmcs->soft_vnmi_blocked = masked;
            vmx->loaded_vmcs->vnmi_blocked_time = 0;
        }
    } else {
        vmx->loaded_vmcs->nmi_known_unmasked = !masked;
        if (masked)
            vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
                      GUEST_INTR_STATE_NMI);
        else
            vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
                    GUEST_INTR_STATE_NMI);
    }
}

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vmx_set_rflags()

void vmx_set_rflags	(	struct kvm_vcpu *	vcpu,
		unsigned long	rflags
	)

Definition at line 1527 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    unsigned long old_rflags;
 
    /*
     * Unlike CR0 and CR4, RFLAGS handling requires checking if the vCPU
     * is an unrestricted guest in order to mark L2 as needing emulation
     * if L1 runs L2 as a restricted guest.
     */
    if (is_unrestricted_guest(vcpu)) {
        kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS);
        vmx->rflags = rflags;
        vmcs_writel(GUEST_RFLAGS, rflags);
        return;
    }
 
    old_rflags = vmx_get_rflags(vcpu);
    vmx->rflags = rflags;
    if (vmx->rmode.vm86_active) {
        vmx->rmode.save_rflags = rflags;
        rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
    }
    vmcs_writel(GUEST_RFLAGS, rflags);
 
    if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM)
        vmx->emulation_required = vmx_emulation_required(vcpu);
}

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vmx_set_virtual_apic_mode()

void vmx_set_virtual_apic_mode

(

struct kvm_vcpu *

vcpu

)

Definition at line 6694 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    u32 sec_exec_control;
 
    if (!lapic_in_kernel(vcpu))
        return;
 
    if (!flexpriority_enabled &&
        !cpu_has_vmx_virtualize_x2apic_mode())
        return;
 
    /* Postpone execution until vmcs01 is the current VMCS. */
    if (is_guest_mode(vcpu)) {
        vmx->nested.change_vmcs01_virtual_apic_mode = true;
        return;
    }
 
    sec_exec_control = secondary_exec_controls_get(vmx);
    sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
                  SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
 
    switch (kvm_get_apic_mode(vcpu)) {
    case LAPIC_MODE_INVALID:
        WARN_ONCE(true, "Invalid local APIC state");
        break;
    case LAPIC_MODE_DISABLED:
        break;
    case LAPIC_MODE_XAPIC:
        if (flexpriority_enabled) {
            sec_exec_control |=
                SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
            kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
 
            /*
             * Flush the TLB, reloading the APIC access page will
             * only do so if its physical address has changed, but
             * the guest may have inserted a non-APIC mapping into
             * the TLB while the APIC access page was disabled.
             */
            kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
        }
        break;
    case LAPIC_MODE_X2APIC:
        if (cpu_has_vmx_virtualize_x2apic_mode())
            sec_exec_control |=
                SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
        break;
    }
    secondary_exec_controls_set(vmx, sec_exec_control);
 
    vmx_update_msr_bitmap_x2apic(vcpu);
}

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vmx_spec_ctrl_restore_host()

void vmx_spec_ctrl_restore_host	(	struct vcpu_vmx *	vmx,
		unsigned int	flags
	)

Definition at line 7192 of file vmx.c.

{
    u64 hostval = this_cpu_read(x86_spec_ctrl_current);
 
    if (!cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL))
        return;
 
    if (flags & VMX_RUN_SAVE_SPEC_CTRL)
        vmx->spec_ctrl = __rdmsr(MSR_IA32_SPEC_CTRL);
 
    /*
     * If the guest/host SPEC_CTRL values differ, restore the host value.
     *
     * For legacy IBRS, the IBRS bit always needs to be written after
     * transitioning from a less privileged predictor mode, regardless of
     * whether the guest/host values differ.
     */
    if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) ||
        vmx->spec_ctrl != hostval)
        native_wrmsrl(MSR_IA32_SPEC_CTRL, hostval);
 
    barrier_nospec();
}

vmx_update_cpu_dirty_logging()

void vmx_update_cpu_dirty_logging

(

struct kvm_vcpu *

vcpu

)

Definition at line 8110 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
 
    if (WARN_ON_ONCE(!enable_pml))
        return;
 
    if (is_guest_mode(vcpu)) {
        vmx->nested.update_vmcs01_cpu_dirty_logging = true;
        return;
    }
 
    /*
     * Note, nr_memslots_dirty_logging can be changed concurrent with this
     * code, but in that case another update request will be made and so
     * the guest will never run with a stale PML value.
     */
    if (atomic_read(&vcpu->kvm->nr_memslots_dirty_logging))
        secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_ENABLE_PML);
    else
        secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_ENABLE_PML);
}

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vmx_update_exception_bitmap()

void vmx_update_exception_bitmap

(

struct kvm_vcpu *

vcpu

)

Definition at line 874 of file vmx.c.

{
    u32 eb;
 
    eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
         (1u << DB_VECTOR) | (1u << AC_VECTOR);
    /*
     * Guest access to VMware backdoor ports could legitimately
     * trigger #GP because of TSS I/O permission bitmap.
     * We intercept those #GP and allow access to them anyway
     * as VMware does.
     */
    if (enable_vmware_backdoor)
        eb |= (1u << GP_VECTOR);
    if ((vcpu->guest_debug &
         (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
        (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
        eb |= 1u << BP_VECTOR;
    if (to_vmx(vcpu)->rmode.vm86_active)
        eb = ~0;
    if (!vmx_need_pf_intercept(vcpu))
        eb &= ~(1u << PF_VECTOR);
 
    /* When we are running a nested L2 guest and L1 specified for it a
     * certain exception bitmap, we must trap the same exceptions and pass
     * them to L1. When running L2, we will only handle the exceptions
     * specified above if L1 did not want them.
     */
    if (is_guest_mode(vcpu))
        eb |= get_vmcs12(vcpu)->exception_bitmap;
    else {
        int mask = 0, match = 0;
 
        if (enable_ept && (eb & (1u << PF_VECTOR))) {
            /*
             * If EPT is enabled, #PF is currently only intercepted
             * if MAXPHYADDR is smaller on the guest than on the
             * host.  In that case we only care about present,
             * non-reserved faults.  For vmcs02, however, PFEC_MASK
             * and PFEC_MATCH are set in prepare_vmcs02_rare.
             */
            mask = PFERR_PRESENT_MASK | PFERR_RSVD_MASK;
            match = PFERR_PRESENT_MASK;
        }
        vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
        vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, match);
    }
 
    /*
     * Disabling xfd interception indicates that dynamic xfeatures
     * might be used in the guest. Always trap #NM in this case
     * to save guest xfd_err timely.
     */
    if (vcpu->arch.xfd_no_write_intercept)
        eb |= (1u << NM_VECTOR);
 
    vmcs_write32(EXCEPTION_BITMAP, eb);
}

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vmx_update_host_rsp()

void vmx_update_host_rsp	(	struct vcpu_vmx *	vmx,
		unsigned long	host_rsp
	)

Definition at line 7184 of file vmx.c.

{
    if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) {
        vmx->loaded_vmcs->host_state.rsp = host_rsp;
        vmcs_writel(HOST_RSP, host_rsp);
    }
}

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vmx_vcpu_load_vmcs()

void vmx_vcpu_load_vmcs	(	struct kvm_vcpu *	vcpu,
		int	cpu,
		struct loaded_vmcs *	buddy
	)

Definition at line 1415 of file vmx.c.

{
    struct vcpu_vmx *vmx = to_vmx(vcpu);
    bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
    struct vmcs *prev;
 
    if (!already_loaded) {
        loaded_vmcs_clear(vmx->loaded_vmcs);
        local_irq_disable();
 
        /*
         * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
         * this cpu's percpu list, otherwise it may not yet be deleted
         * from its previous cpu's percpu list.  Pairs with the
         * smb_wmb() in __loaded_vmcs_clear().
         */
        smp_rmb();
 
        list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
             &per_cpu(loaded_vmcss_on_cpu, cpu));
        local_irq_enable();
    }
 
    prev = per_cpu(current_vmcs, cpu);
    if (prev != vmx->loaded_vmcs->vmcs) {
        per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
        vmcs_load(vmx->loaded_vmcs->vmcs);
 
        /*
         * No indirect branch prediction barrier needed when switching
         * the active VMCS within a vCPU, unless IBRS is advertised to
         * the vCPU.  To minimize the number of IBPBs executed, KVM
         * performs IBPB on nested VM-Exit (a single nested transition
         * may switch the active VMCS multiple times).
         */
        if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
            indirect_branch_prediction_barrier();
    }
 
    if (!already_loaded) {
        void *gdt = get_current_gdt_ro();
 
        /*
         * Flush all EPTP/VPID contexts, the new pCPU may have stale
         * TLB entries from its previous association with the vCPU.
         */
        kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 
        /*
         * Linux uses per-cpu TSS and GDT, so set these when switching
         * processors.  See 22.2.4.
         */
        vmcs_writel(HOST_TR_BASE,
                (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
        vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
 
        if (IS_ENABLED(CONFIG_IA32_EMULATION) || IS_ENABLED(CONFIG_X86_32)) {
            /* 22.2.3 */
            vmcs_writel(HOST_IA32_SYSENTER_ESP,
                    (unsigned long)(cpu_entry_stack(cpu) + 1));
        }
 
        vmx->loaded_vmcs->cpu = cpu;
    }
}

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