vgic.h File Reference

#include <linux/irqchip/arm-gic-common.h>
#include <asm/kvm_mmu.h>

Include dependency graph for vgic.h:

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Go to the source code of this file.

Classes
struct	vgic_vmcr
struct	vgic_reg_attr

Macros
#define	PRODUCT_ID_KVM   0x4b /* ASCII code K */
#define	IMPLEMENTER_ARM   0x43b
#define	VGIC_ADDR_UNDEF   (-1)
#define	IS_VGIC_ADDR_UNDEF(_x)   ((_x) == VGIC_ADDR_UNDEF)
#define	INTERRUPT_ID_BITS_SPIS   10
#define	INTERRUPT_ID_BITS_ITS   16
#define	VGIC_PRI_BITS   5
#define	vgic_irq_is_sgi(intid)   ((intid) < VGIC_NR_SGIS)
#define	VGIC_AFFINITY_0_SHIFT   0
#define	VGIC_AFFINITY_0_MASK   (0xffUL << VGIC_AFFINITY_0_SHIFT)
#define	VGIC_AFFINITY_1_SHIFT   8
#define	VGIC_AFFINITY_1_MASK   (0xffUL << VGIC_AFFINITY_1_SHIFT)
#define	VGIC_AFFINITY_2_SHIFT   16
#define	VGIC_AFFINITY_2_MASK   (0xffUL << VGIC_AFFINITY_2_SHIFT)
#define	VGIC_AFFINITY_3_SHIFT   24
#define	VGIC_AFFINITY_3_MASK   (0xffUL << VGIC_AFFINITY_3_SHIFT)
#define	VGIC_AFFINITY_LEVEL(reg, level)
#define	VGIC_TO_MPIDR(val)
#define	KVM_REG_ARM_VGIC_SYSREG_OP0_MASK   0x000000000000c000
#define	KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT   14
#define	KVM_REG_ARM_VGIC_SYSREG_OP1_MASK   0x0000000000003800
#define	KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT   11
#define	KVM_REG_ARM_VGIC_SYSREG_CRN_MASK   0x0000000000000780
#define	KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT   7
#define	KVM_REG_ARM_VGIC_SYSREG_CRM_MASK   0x0000000000000078
#define	KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT   3
#define	KVM_REG_ARM_VGIC_SYSREG_OP2_MASK   0x0000000000000007
#define	KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT   0
#define	KVM_DEV_ARM_VGIC_SYSREG_MASK
#define	KVM_ITS_CTE_VALID_SHIFT   63
#define	KVM_ITS_CTE_VALID_MASK   BIT_ULL(63)
#define	KVM_ITS_CTE_RDBASE_SHIFT   16
#define	KVM_ITS_CTE_ICID_MASK   GENMASK_ULL(15, 0)
#define	KVM_ITS_ITE_NEXT_SHIFT   48
#define	KVM_ITS_ITE_PINTID_SHIFT   16
#define	KVM_ITS_ITE_PINTID_MASK   GENMASK_ULL(47, 16)
#define	KVM_ITS_ITE_ICID_MASK   GENMASK_ULL(15, 0)
#define	KVM_ITS_DTE_VALID_SHIFT   63
#define	KVM_ITS_DTE_VALID_MASK   BIT_ULL(63)
#define	KVM_ITS_DTE_NEXT_SHIFT   49
#define	KVM_ITS_DTE_NEXT_MASK   GENMASK_ULL(62, 49)
#define	KVM_ITS_DTE_ITTADDR_SHIFT   5
#define	KVM_ITS_DTE_ITTADDR_MASK   GENMASK_ULL(48, 5)
#define	KVM_ITS_DTE_SIZE_MASK   GENMASK_ULL(4, 0)
#define	KVM_ITS_L1E_VALID_MASK   BIT_ULL(63)
#define	KVM_ITS_L1E_ADDR_MASK   GENMASK_ULL(51, 16)
#define	KVM_VGIC_V3_RDIST_INDEX_MASK   GENMASK_ULL(11, 0)
#define	KVM_VGIC_V3_RDIST_FLAGS_MASK   GENMASK_ULL(15, 12)
#define	KVM_VGIC_V3_RDIST_FLAGS_SHIFT   12
#define	KVM_VGIC_V3_RDIST_BASE_MASK   GENMASK_ULL(51, 16)
#define	KVM_VGIC_V3_RDIST_COUNT_MASK   GENMASK_ULL(63, 52)
#define	KVM_VGIC_V3_RDIST_COUNT_SHIFT   52
#define	DEBUG_SPINLOCK_BUG_ON(p)

Functions
static u32	vgic_get_implementation_rev (struct kvm_vcpu *vcpu)
static bool	irq_is_pending (struct vgic_irq *irq)
static bool	vgic_irq_is_mapped_level (struct vgic_irq *irq)
static int	vgic_irq_get_lr_count (struct vgic_irq *irq)
static bool	vgic_irq_is_multi_sgi (struct vgic_irq *irq)
static int	vgic_write_guest_lock (struct kvm *kvm, gpa_t gpa, const void *data, unsigned long len)
int	vgic_v3_parse_attr (struct kvm_device *dev, struct kvm_device_attr *attr, struct vgic_reg_attr *reg_attr)
int	vgic_v2_parse_attr (struct kvm_device *dev, struct kvm_device_attr *attr, struct vgic_reg_attr *reg_attr)
const struct vgic_register_region *	vgic_get_mmio_region (struct kvm_vcpu *vcpu, struct vgic_io_device *iodev, gpa_t addr, int len)
struct vgic_irq *	vgic_get_irq (struct kvm *kvm, struct kvm_vcpu *vcpu, u32 intid)
void	__vgic_put_lpi_locked (struct kvm *kvm, struct vgic_irq *irq)
void	vgic_put_irq (struct kvm *kvm, struct vgic_irq *irq)
bool	vgic_get_phys_line_level (struct vgic_irq *irq)
void	vgic_irq_set_phys_pending (struct vgic_irq *irq, bool pending)
void	vgic_irq_set_phys_active (struct vgic_irq *irq, bool active)
bool	vgic_queue_irq_unlock (struct kvm *kvm, struct vgic_irq *irq, unsigned long flags)
void	vgic_kick_vcpus (struct kvm *kvm)
void	vgic_irq_handle_resampling (struct vgic_irq *irq, bool lr_deactivated, bool lr_pending)
int	vgic_check_iorange (struct kvm *kvm, phys_addr_t ioaddr, phys_addr_t addr, phys_addr_t alignment, phys_addr_t size)
void	vgic_v2_fold_lr_state (struct kvm_vcpu *vcpu)
void	vgic_v2_populate_lr (struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
void	vgic_v2_clear_lr (struct kvm_vcpu *vcpu, int lr)
void	vgic_v2_set_underflow (struct kvm_vcpu *vcpu)
int	vgic_v2_has_attr_regs (struct kvm_device *dev, struct kvm_device_attr *attr)
int	vgic_v2_dist_uaccess (struct kvm_vcpu *vcpu, bool is_write, int offset, u32 *val)
int	vgic_v2_cpuif_uaccess (struct kvm_vcpu *vcpu, bool is_write, int offset, u32 *val)
void	vgic_v2_set_vmcr (struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
void	vgic_v2_get_vmcr (struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
void	vgic_v2_enable (struct kvm_vcpu *vcpu)
int	vgic_v2_probe (const struct gic_kvm_info *info)
int	vgic_v2_map_resources (struct kvm *kvm)
int	vgic_register_dist_iodev (struct kvm *kvm, gpa_t dist_base_address, enum vgic_type)
void	vgic_v2_init_lrs (void)
void	vgic_v2_load (struct kvm_vcpu *vcpu)
void	vgic_v2_put (struct kvm_vcpu *vcpu)
void	vgic_v2_vmcr_sync (struct kvm_vcpu *vcpu)
void	vgic_v2_save_state (struct kvm_vcpu *vcpu)
void	vgic_v2_restore_state (struct kvm_vcpu *vcpu)
static void	vgic_get_irq_kref (struct vgic_irq *irq)
void	vgic_v3_fold_lr_state (struct kvm_vcpu *vcpu)
void	vgic_v3_populate_lr (struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
void	vgic_v3_clear_lr (struct kvm_vcpu *vcpu, int lr)
void	vgic_v3_set_underflow (struct kvm_vcpu *vcpu)
void	vgic_v3_set_vmcr (struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
void	vgic_v3_get_vmcr (struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
void	vgic_v3_enable (struct kvm_vcpu *vcpu)
int	vgic_v3_probe (const struct gic_kvm_info *info)
int	vgic_v3_map_resources (struct kvm *kvm)
int	vgic_v3_lpi_sync_pending_status (struct kvm *kvm, struct vgic_irq *irq)
int	vgic_v3_save_pending_tables (struct kvm *kvm)
int	vgic_v3_set_redist_base (struct kvm *kvm, u32 index, u64 addr, u32 count)
int	vgic_register_redist_iodev (struct kvm_vcpu *vcpu)
void	vgic_unregister_redist_iodev (struct kvm_vcpu *vcpu)
bool	vgic_v3_check_base (struct kvm *kvm)
void	vgic_v3_load (struct kvm_vcpu *vcpu)
void	vgic_v3_put (struct kvm_vcpu *vcpu)
void	vgic_v3_vmcr_sync (struct kvm_vcpu *vcpu)
bool	vgic_has_its (struct kvm *kvm)
int	kvm_vgic_register_its_device (void)
void	vgic_enable_lpis (struct kvm_vcpu *vcpu)
void	vgic_flush_pending_lpis (struct kvm_vcpu *vcpu)
int	vgic_its_inject_msi (struct kvm *kvm, struct kvm_msi *msi)
int	vgic_v3_has_attr_regs (struct kvm_device *dev, struct kvm_device_attr *attr)
int	vgic_v3_dist_uaccess (struct kvm_vcpu *vcpu, bool is_write, int offset, u32 *val)
int	vgic_v3_redist_uaccess (struct kvm_vcpu *vcpu, bool is_write, int offset, u32 *val)
int	vgic_v3_cpu_sysregs_uaccess (struct kvm_vcpu *vcpu, struct kvm_device_attr *attr, bool is_write)
int	vgic_v3_has_cpu_sysregs_attr (struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
int	vgic_v3_line_level_info_uaccess (struct kvm_vcpu *vcpu, bool is_write, u32 intid, u32 *val)
int	kvm_register_vgic_device (unsigned long type)
void	vgic_set_vmcr (struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
void	vgic_get_vmcr (struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
int	vgic_lazy_init (struct kvm *kvm)
int	vgic_init (struct kvm *kvm)
void	vgic_debug_init (struct kvm *kvm)
void	vgic_debug_destroy (struct kvm *kvm)
static int	vgic_v3_max_apr_idx (struct kvm_vcpu *vcpu)
static bool	vgic_v3_redist_region_full (struct vgic_redist_region *region)
struct vgic_redist_region *	vgic_v3_rdist_free_slot (struct list_head *rdregs)
static size_t	vgic_v3_rd_region_size (struct kvm *kvm, struct vgic_redist_region *rdreg)
struct vgic_redist_region *	vgic_v3_rdist_region_from_index (struct kvm *kvm, u32 index)
void	vgic_v3_free_redist_region (struct vgic_redist_region *rdreg)
bool	vgic_v3_rdist_overlap (struct kvm *kvm, gpa_t base, size_t size)
static bool	vgic_dist_overlap (struct kvm *kvm, gpa_t base, size_t size)
bool	vgic_lpis_enabled (struct kvm_vcpu *vcpu)
int	vgic_copy_lpi_list (struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr)
int	vgic_its_resolve_lpi (struct kvm *kvm, struct vgic_its *its, u32 devid, u32 eventid, struct vgic_irq **irq)
struct vgic_its *	vgic_msi_to_its (struct kvm *kvm, struct kvm_msi *msi)
int	vgic_its_inject_cached_translation (struct kvm *kvm, struct kvm_msi *msi)
void	vgic_lpi_translation_cache_init (struct kvm *kvm)
void	vgic_lpi_translation_cache_destroy (struct kvm *kvm)
void	vgic_its_invalidate_cache (struct kvm *kvm)
int	vgic_its_inv_lpi (struct kvm *kvm, struct vgic_irq *irq)
int	vgic_its_invall (struct kvm_vcpu *vcpu)
bool	vgic_supports_direct_msis (struct kvm *kvm)
int	vgic_v4_init (struct kvm *kvm)
void	vgic_v4_teardown (struct kvm *kvm)
void	vgic_v4_configure_vsgis (struct kvm *kvm)
void	vgic_v4_get_vlpi_state (struct vgic_irq *irq, bool *val)
int	vgic_v4_request_vpe_irq (struct kvm_vcpu *vcpu, int irq)

Macro Definition Documentation

DEBUG_SPINLOCK_BUG_ON

#define DEBUG_SPINLOCK_BUG_ON

(

p

)

Definition at line 99 of file vgic.h.

IMPLEMENTER_ARM

#define IMPLEMENTER_ARM   0x43b

Definition at line 12 of file vgic.h.

INTERRUPT_ID_BITS_ITS

#define INTERRUPT_ID_BITS_ITS   16

Definition at line 18 of file vgic.h.

INTERRUPT_ID_BITS_SPIS

#define INTERRUPT_ID_BITS_SPIS   10

Definition at line 17 of file vgic.h.

IS_VGIC_ADDR_UNDEF

#define IS_VGIC_ADDR_UNDEF

(

_x

)

((_x) == VGIC_ADDR_UNDEF)

Definition at line 15 of file vgic.h.

KVM_DEV_ARM_VGIC_SYSREG_MASK

#define KVM_DEV_ARM_VGIC_SYSREG_MASK

Value:

                      (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
                      KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
                      KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
                      KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
                      KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)

Definition at line 60 of file vgic.h.

KVM_ITS_CTE_ICID_MASK

#define KVM_ITS_CTE_ICID_MASK   GENMASK_ULL(15, 0)

Definition at line 73 of file vgic.h.

KVM_ITS_CTE_RDBASE_SHIFT

#define KVM_ITS_CTE_RDBASE_SHIFT   16

Definition at line 72 of file vgic.h.

KVM_ITS_CTE_VALID_MASK

#define KVM_ITS_CTE_VALID_MASK   BIT_ULL(63)

Definition at line 71 of file vgic.h.

KVM_ITS_CTE_VALID_SHIFT

#define KVM_ITS_CTE_VALID_SHIFT   63

Definition at line 70 of file vgic.h.

KVM_ITS_DTE_ITTADDR_MASK

#define KVM_ITS_DTE_ITTADDR_MASK   GENMASK_ULL(48, 5)

Definition at line 83 of file vgic.h.

KVM_ITS_DTE_ITTADDR_SHIFT

#define KVM_ITS_DTE_ITTADDR_SHIFT   5

Definition at line 82 of file vgic.h.

KVM_ITS_DTE_NEXT_MASK

#define KVM_ITS_DTE_NEXT_MASK   GENMASK_ULL(62, 49)

Definition at line 81 of file vgic.h.

KVM_ITS_DTE_NEXT_SHIFT

#define KVM_ITS_DTE_NEXT_SHIFT   49

Definition at line 80 of file vgic.h.

KVM_ITS_DTE_SIZE_MASK

#define KVM_ITS_DTE_SIZE_MASK   GENMASK_ULL(4, 0)

Definition at line 84 of file vgic.h.

KVM_ITS_DTE_VALID_MASK

#define KVM_ITS_DTE_VALID_MASK   BIT_ULL(63)

Definition at line 79 of file vgic.h.

KVM_ITS_DTE_VALID_SHIFT

#define KVM_ITS_DTE_VALID_SHIFT   63

Definition at line 78 of file vgic.h.

KVM_ITS_ITE_ICID_MASK

#define KVM_ITS_ITE_ICID_MASK   GENMASK_ULL(15, 0)

Definition at line 77 of file vgic.h.

KVM_ITS_ITE_NEXT_SHIFT

#define KVM_ITS_ITE_NEXT_SHIFT   48

Definition at line 74 of file vgic.h.

KVM_ITS_ITE_PINTID_MASK

#define KVM_ITS_ITE_PINTID_MASK   GENMASK_ULL(47, 16)

Definition at line 76 of file vgic.h.

KVM_ITS_ITE_PINTID_SHIFT

#define KVM_ITS_ITE_PINTID_SHIFT   16

Definition at line 75 of file vgic.h.

KVM_ITS_L1E_ADDR_MASK

#define KVM_ITS_L1E_ADDR_MASK   GENMASK_ULL(51, 16)

Definition at line 87 of file vgic.h.

KVM_ITS_L1E_VALID_MASK

#define KVM_ITS_L1E_VALID_MASK   BIT_ULL(63)

Definition at line 85 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_CRM_MASK

#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK   0x0000000000000078

Definition at line 55 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT

#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT   3

Definition at line 56 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_CRN_MASK

#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK   0x0000000000000780

Definition at line 53 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT

#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT   7

Definition at line 54 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_OP0_MASK

#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK   0x000000000000c000

Definition at line 49 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT

#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT   14

Definition at line 50 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_OP1_MASK

#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK   0x0000000000003800

Definition at line 51 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT

#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT   11

Definition at line 52 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_OP2_MASK

#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK   0x0000000000000007

Definition at line 57 of file vgic.h.

KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT

#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT   0

Definition at line 58 of file vgic.h.

KVM_VGIC_V3_RDIST_BASE_MASK

#define KVM_VGIC_V3_RDIST_BASE_MASK   GENMASK_ULL(51, 16)

Definition at line 92 of file vgic.h.

KVM_VGIC_V3_RDIST_COUNT_MASK

#define KVM_VGIC_V3_RDIST_COUNT_MASK   GENMASK_ULL(63, 52)

Definition at line 93 of file vgic.h.

KVM_VGIC_V3_RDIST_COUNT_SHIFT

#define KVM_VGIC_V3_RDIST_COUNT_SHIFT   52

Definition at line 94 of file vgic.h.

KVM_VGIC_V3_RDIST_FLAGS_MASK

#define KVM_VGIC_V3_RDIST_FLAGS_MASK   GENMASK_ULL(15, 12)

Definition at line 90 of file vgic.h.

KVM_VGIC_V3_RDIST_FLAGS_SHIFT

#define KVM_VGIC_V3_RDIST_FLAGS_SHIFT   12

Definition at line 91 of file vgic.h.

KVM_VGIC_V3_RDIST_INDEX_MASK

#define KVM_VGIC_V3_RDIST_INDEX_MASK   GENMASK_ULL(11, 0)

Definition at line 89 of file vgic.h.

PRODUCT_ID_KVM

#define PRODUCT_ID_KVM   0x4b /* ASCII code K */

Definition at line 11 of file vgic.h.

VGIC_ADDR_UNDEF

#define VGIC_ADDR_UNDEF   (-1)

Definition at line 14 of file vgic.h.

VGIC_AFFINITY_0_MASK

#define VGIC_AFFINITY_0_MASK   (0xffUL << VGIC_AFFINITY_0_SHIFT)

Definition at line 24 of file vgic.h.

VGIC_AFFINITY_0_SHIFT

#define VGIC_AFFINITY_0_SHIFT   0

Definition at line 23 of file vgic.h.

VGIC_AFFINITY_1_MASK

#define VGIC_AFFINITY_1_MASK   (0xffUL << VGIC_AFFINITY_1_SHIFT)

Definition at line 26 of file vgic.h.

VGIC_AFFINITY_1_SHIFT

#define VGIC_AFFINITY_1_SHIFT   8

Definition at line 25 of file vgic.h.

VGIC_AFFINITY_2_MASK

#define VGIC_AFFINITY_2_MASK   (0xffUL << VGIC_AFFINITY_2_SHIFT)

Definition at line 28 of file vgic.h.

VGIC_AFFINITY_2_SHIFT

#define VGIC_AFFINITY_2_SHIFT   16

Definition at line 27 of file vgic.h.

VGIC_AFFINITY_3_MASK

#define VGIC_AFFINITY_3_MASK   (0xffUL << VGIC_AFFINITY_3_SHIFT)

Definition at line 30 of file vgic.h.

VGIC_AFFINITY_3_SHIFT

#define VGIC_AFFINITY_3_SHIFT   24

Definition at line 29 of file vgic.h.

VGIC_AFFINITY_LEVEL

#define VGIC_AFFINITY_LEVEL	(		reg,
			level
	)

Value:

    ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
    >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))

Definition at line 32 of file vgic.h.

vgic_irq_is_sgi

#define vgic_irq_is_sgi

(

intid

)

((intid) < VGIC_NR_SGIS)

Definition at line 21 of file vgic.h.

VGIC_PRI_BITS

#define VGIC_PRI_BITS   5

Definition at line 19 of file vgic.h.

VGIC_TO_MPIDR

#define VGIC_TO_MPIDR

(

val

)

Value:

                (VGIC_AFFINITY_LEVEL(val, 0) | \
                VGIC_AFFINITY_LEVEL(val, 1) | \
                VGIC_AFFINITY_LEVEL(val, 2) | \
                VGIC_AFFINITY_LEVEL(val, 3))

Definition at line 40 of file vgic.h.

Function Documentation

__vgic_put_lpi_locked()

void __vgic_put_lpi_locked	(	struct kvm *	kvm,
		struct vgic_irq *	irq
	)

Definition at line 126 of file vgic.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
 
    if (!kref_put(&irq->refcount, vgic_irq_release))
        return;
 
    list_del(&irq->lpi_list);
    dist->lpi_list_count--;
 
    kfree(irq);
}

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irq_is_pending()

static bool irq_is_pending ( struct vgic_irq *  irq )

inlinestatic

Definition at line 108 of file vgic.h.

{
    if (irq->config == VGIC_CONFIG_EDGE)
        return irq->pending_latch;
    else
        return irq->pending_latch || irq->line_level;
}

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kvm_register_vgic_device()

int kvm_register_vgic_device

(

unsigned long

type

)

Definition at line 316 of file vgic-kvm-device.c.

{
    int ret = -ENODEV;
 
    switch (type) {
    case KVM_DEV_TYPE_ARM_VGIC_V2:
        ret = kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
                          KVM_DEV_TYPE_ARM_VGIC_V2);
        break;
    case KVM_DEV_TYPE_ARM_VGIC_V3:
        ret = kvm_register_device_ops(&kvm_arm_vgic_v3_ops,
                          KVM_DEV_TYPE_ARM_VGIC_V3);
 
        if (ret)
            break;
        ret = kvm_vgic_register_its_device();
        break;
    }
 
    return ret;
}

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kvm_vgic_register_its_device()

int kvm_vgic_register_its_device

(

void

)

Definition at line 2914 of file vgic-its.c.

{
    return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
                       KVM_DEV_TYPE_ARM_VGIC_ITS);
}

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vgic_check_iorange()

int vgic_check_iorange	(	struct kvm *	kvm,
		phys_addr_t	ioaddr,
		phys_addr_t	addr,
		phys_addr_t	alignment,
		phys_addr_t	size
	)

Definition at line 17 of file vgic-kvm-device.c.

{
    if (!IS_VGIC_ADDR_UNDEF(ioaddr))
        return -EEXIST;
 
    if (!IS_ALIGNED(addr, alignment) || !IS_ALIGNED(size, alignment))
        return -EINVAL;
 
    if (addr + size < addr)
        return -EINVAL;
 
    if (addr & ~kvm_phys_mask(&kvm->arch.mmu) ||
        (addr + size) > kvm_phys_size(&kvm->arch.mmu))
        return -E2BIG;
 
    return 0;
}

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vgic_copy_lpi_list()

int vgic_copy_lpi_list	(	struct kvm *	kvm,
		struct kvm_vcpu *	vcpu,
		u32 **	intid_ptr
	)

Definition at line 319 of file vgic-its.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    struct vgic_irq *irq;
    unsigned long flags;
    u32 *intids;
    int irq_count, i = 0;
 
    /*
     * There is an obvious race between allocating the array and LPIs
     * being mapped/unmapped. If we ended up here as a result of a
     * command, we're safe (locks are held, preventing another
     * command). If coming from another path (such as enabling LPIs),
     * we must be careful not to overrun the array.
     */
    irq_count = READ_ONCE(dist->lpi_list_count);
    intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL_ACCOUNT);
    if (!intids)
        return -ENOMEM;
 
    raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
    list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
        if (i == irq_count)
            break;
        /* We don't need to "get" the IRQ, as we hold the list lock. */
        if (vcpu && irq->target_vcpu != vcpu)
            continue;
        intids[i++] = irq->intid;
    }
    raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
 
    *intid_ptr = intids;
    return i;
}

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vgic_debug_destroy()

void vgic_debug_destroy

(

struct kvm *

kvm

)

Definition at line 278 of file vgic-debug.c.

{
}

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vgic_debug_init()

void vgic_debug_init

(

struct kvm *

kvm

)

Definition at line 272 of file vgic-debug.c.

{
    debugfs_create_file("vgic-state", 0444, kvm->debugfs_dentry, kvm,
                &vgic_debug_fops);
}

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vgic_dist_overlap()

static bool vgic_dist_overlap ( struct kvm *  kvm, gpa_t  base, size_t  size  )

inlinestatic

Definition at line 317 of file vgic.h.

{
    struct vgic_dist *d = &kvm->arch.vgic;
 
    return (base + size > d->vgic_dist_base) &&
        (base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE);
}

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vgic_enable_lpis()

void vgic_enable_lpis

(

struct kvm_vcpu *

vcpu

)

Definition at line 1866 of file vgic-its.c.

{
    if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ))
        its_sync_lpi_pending_table(vcpu);
}

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vgic_flush_pending_lpis()

void vgic_flush_pending_lpis

(

struct kvm_vcpu *

vcpu

)

Definition at line 152 of file vgic.c.

{
    struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
    struct vgic_irq *irq, *tmp;
    unsigned long flags;
 
    raw_spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags);
 
    list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
        if (irq->intid >= VGIC_MIN_LPI) {
            raw_spin_lock(&irq->irq_lock);
            list_del(&irq->ap_list);
            irq->vcpu = NULL;
            raw_spin_unlock(&irq->irq_lock);
            vgic_put_irq(vcpu->kvm, irq);
        }
    }
 
    raw_spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags);
}

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vgic_get_implementation_rev()

static u32 vgic_get_implementation_rev ( struct kvm_vcpu *  vcpu )

inlinestatic

Definition at line 102 of file vgic.h.

{
    return vcpu->kvm->arch.vgic.implementation_rev;
}

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vgic_get_irq()

struct vgic_irq* vgic_get_irq	(	struct kvm *	kvm,
		struct kvm_vcpu *	vcpu,
		u32	intid
	)

Definition at line 92 of file vgic.c.

{
    /* SGIs and PPIs */
    if (intid <= VGIC_MAX_PRIVATE) {
        intid = array_index_nospec(intid, VGIC_MAX_PRIVATE + 1);
        return &vcpu->arch.vgic_cpu.private_irqs[intid];
    }
 
    /* SPIs */
    if (intid < (kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) {
        intid = array_index_nospec(intid, kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS);
        return &kvm->arch.vgic.spis[intid - VGIC_NR_PRIVATE_IRQS];
    }
 
    /* LPIs */
    if (intid >= VGIC_MIN_LPI)
        return vgic_get_lpi(kvm, intid);
 
    return NULL;
}

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vgic_get_irq_kref()

static void vgic_get_irq_kref ( struct vgic_irq *  irq )

inlinestatic

Definition at line 223 of file vgic.h.

{
    if (irq->intid < VGIC_MIN_LPI)
        return;
 
    kref_get(&irq->refcount);
}

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vgic_get_mmio_region()

const struct vgic_register_region* vgic_get_mmio_region	(	struct kvm_vcpu *	vcpu,
		struct vgic_io_device *	iodev,
		gpa_t	addr,
		int	len
	)

Definition at line 950 of file vgic-mmio.c.

{
    const struct vgic_register_region *region;
 
    region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
                       addr - iodev->base_addr);
    if (!region || !check_region(vcpu->kvm, region, addr, len))
        return NULL;
 
    return region;
}

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vgic_get_phys_line_level()

bool vgic_get_phys_line_level

(

struct vgic_irq *

irq

)

Definition at line 180 of file vgic.c.

{
    bool line_level;
 
    BUG_ON(!irq->hw);
 
    if (irq->ops && irq->ops->get_input_level)
        return irq->ops->get_input_level(irq->intid);
 
    WARN_ON(irq_get_irqchip_state(irq->host_irq,
                      IRQCHIP_STATE_PENDING,
                      &line_level));
    return line_level;
}

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vgic_get_vmcr()

void vgic_get_vmcr	(	struct kvm_vcpu *	vcpu,
		struct vgic_vmcr *	vmcr
	)

Definition at line 851 of file vgic-mmio.c.

{
    if (kvm_vgic_global_state.type == VGIC_V2)
        vgic_v2_get_vmcr(vcpu, vmcr);
    else
        vgic_v3_get_vmcr(vcpu, vmcr);
}

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vgic_has_its()

bool vgic_has_its

(

struct kvm *

kvm

)

Definition at line 41 of file vgic-mmio-v3.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
 
    if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
        return false;
 
    return dist->has_its;
}

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vgic_init()

int vgic_init

(

struct kvm *

kvm

)

Definition at line 262 of file vgic-init.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    struct kvm_vcpu *vcpu;
    int ret = 0, i;
    unsigned long idx;
 
    lockdep_assert_held(&kvm->arch.config_lock);
 
    if (vgic_initialized(kvm))
        return 0;
 
    /* Are we also in the middle of creating a VCPU? */
    if (kvm->created_vcpus != atomic_read(&kvm->online_vcpus))
        return -EBUSY;
 
    /* freeze the number of spis */
    if (!dist->nr_spis)
        dist->nr_spis = VGIC_NR_IRQS_LEGACY - VGIC_NR_PRIVATE_IRQS;
 
    ret = kvm_vgic_dist_init(kvm, dist->nr_spis);
    if (ret)
        goto out;
 
    /* Initialize groups on CPUs created before the VGIC type was known */
    kvm_for_each_vcpu(idx, vcpu, kvm) {
        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 
        for (i = 0; i < VGIC_NR_PRIVATE_IRQS; i++) {
            struct vgic_irq *irq = &vgic_cpu->private_irqs[i];
            switch (dist->vgic_model) {
            case KVM_DEV_TYPE_ARM_VGIC_V3:
                irq->group = 1;
                irq->mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
                break;
            case KVM_DEV_TYPE_ARM_VGIC_V2:
                irq->group = 0;
                irq->targets = 1U << idx;
                break;
            default:
                ret = -EINVAL;
                goto out;
            }
        }
    }
 
    if (vgic_has_its(kvm))
        vgic_lpi_translation_cache_init(kvm);
 
    /*
     * If we have GICv4.1 enabled, unconditionnaly request enable the
     * v4 support so that we get HW-accelerated vSGIs. Otherwise, only
     * enable it if we present a virtual ITS to the guest.
     */
    if (vgic_supports_direct_msis(kvm)) {
        ret = vgic_v4_init(kvm);
        if (ret)
            goto out;
    }
 
    kvm_for_each_vcpu(idx, vcpu, kvm)
        kvm_vgic_vcpu_enable(vcpu);
 
    ret = kvm_vgic_setup_default_irq_routing(kvm);
    if (ret)
        goto out;
 
    vgic_debug_init(kvm);
 
    /*
     * If userspace didn't set the GIC implementation revision,
     * default to the latest and greatest. You know want it.
     */
    if (!dist->implementation_rev)
        dist->implementation_rev = KVM_VGIC_IMP_REV_LATEST;
    dist->initialized = true;
 
out:
    return ret;
}

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vgic_irq_get_lr_count()

static int vgic_irq_get_lr_count ( struct vgic_irq *  irq )

inlinestatic

Definition at line 121 of file vgic.h.

{
    /* Account for the active state as an interrupt */
    if (vgic_irq_is_sgi(irq->intid) && irq->source)
        return hweight8(irq->source) + irq->active;
 
    return irq_is_pending(irq) || irq->active;
}

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vgic_irq_handle_resampling()

void vgic_irq_handle_resampling	(	struct vgic_irq *	irq,
		bool	lr_deactivated,
		bool	lr_pending
	)

Definition at line 1060 of file vgic.c.

{
    if (vgic_irq_is_mapped_level(irq)) {
        bool resample = false;
 
        if (unlikely(vgic_irq_needs_resampling(irq))) {
            resample = !(irq->active || irq->pending_latch);
        } else if (lr_pending || (lr_deactivated && irq->line_level)) {
            irq->line_level = vgic_get_phys_line_level(irq);
            resample = !irq->line_level;
        }
 
        if (resample)
            vgic_irq_set_phys_active(irq, false);
    }
}

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vgic_irq_is_mapped_level()

static bool vgic_irq_is_mapped_level ( struct vgic_irq *  irq )

inlinestatic

Definition at line 116 of file vgic.h.

{
    return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
}

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vgic_irq_is_multi_sgi()

static bool vgic_irq_is_multi_sgi ( struct vgic_irq *  irq )

inlinestatic

Definition at line 130 of file vgic.h.

{
    return vgic_irq_get_lr_count(irq) > 1;
}

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vgic_irq_set_phys_active()

void vgic_irq_set_phys_active	(	struct vgic_irq *	irq,
		bool	active
	)

Definition at line 196 of file vgic.c.

{
 
    BUG_ON(!irq->hw);
    WARN_ON(irq_set_irqchip_state(irq->host_irq,
                      IRQCHIP_STATE_ACTIVE,
                      active));
}

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vgic_irq_set_phys_pending()

void vgic_irq_set_phys_pending	(	struct vgic_irq *	irq,
		bool	pending
	)

Definition at line 173 of file vgic.c.

{
    WARN_ON(irq_set_irqchip_state(irq->host_irq,
                      IRQCHIP_STATE_PENDING,
                      pending));
}

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vgic_its_inject_cached_translation()

int vgic_its_inject_cached_translation	(	struct kvm *	kvm,
		struct kvm_msi *	msi
	)

Definition at line 765 of file vgic-its.c.

{
    struct vgic_irq *irq;
    unsigned long flags;
    phys_addr_t db;
 
    db = (u64)msi->address_hi << 32 | msi->address_lo;
    irq = vgic_its_check_cache(kvm, db, msi->devid, msi->data);
    if (!irq)
        return -EWOULDBLOCK;
 
    raw_spin_lock_irqsave(&irq->irq_lock, flags);
    irq->pending_latch = true;
    vgic_queue_irq_unlock(kvm, irq, flags);
    vgic_put_irq(kvm, irq);
 
    return 0;
}

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vgic_its_inject_msi()

int vgic_its_inject_msi	(	struct kvm *	kvm,
		struct kvm_msi *	msi
	)

Definition at line 790 of file vgic-its.c.

{
    struct vgic_its *its;
    int ret;
 
    if (!vgic_its_inject_cached_translation(kvm, msi))
        return 1;
 
    its = vgic_msi_to_its(kvm, msi);
    if (IS_ERR(its))
        return PTR_ERR(its);
 
    mutex_lock(&its->its_lock);
    ret = vgic_its_trigger_msi(kvm, its, msi->devid, msi->data);
    mutex_unlock(&its->its_lock);
 
    if (ret < 0)
        return ret;
 
    /*
     * KVM_SIGNAL_MSI demands a return value > 0 for success and 0
     * if the guest has blocked the MSI. So we map any LPI mapping
     * related error to that.
     */
    if (ret)
        return 0;
    else
        return 1;
}

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vgic_its_inv_lpi()

int vgic_its_inv_lpi	(	struct kvm *	kvm,
		struct vgic_irq *	irq
	)

Definition at line 1323 of file vgic-its.c.

{
    return update_lpi_config(kvm, irq, NULL, true);
}

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vgic_its_invalidate_cache()

void vgic_its_invalidate_cache

(

struct kvm *

kvm

)

Definition at line 659 of file vgic-its.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    struct vgic_translation_cache_entry *cte;
    unsigned long flags;
 
    raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
 
    list_for_each_entry(cte, &dist->lpi_translation_cache, entry) {
        /*
         * If we hit a NULL entry, there is nothing after this
         * point.
         */
        if (!cte->irq)
            break;
 
        __vgic_put_lpi_locked(kvm, cte->irq);
        cte->irq = NULL;
    }
 
    raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
}

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vgic_its_invall()

int vgic_its_invall

(

struct kvm_vcpu *

vcpu

)

vgic_its_invall - invalidate all LPIs targetting a given vcpu @vcpu: the vcpu for which the RD is targetted by an invalidation

Contrary to the INVALL command, this targets a RD instead of a collection, and we don't need to hold the its_lock, since no ITS is involved here.

Definition at line 1355 of file vgic-its.c.

{
    struct kvm *kvm = vcpu->kvm;
    int irq_count, i = 0;
    u32 *intids;
 
    irq_count = vgic_copy_lpi_list(kvm, vcpu, &intids);
    if (irq_count < 0)
        return irq_count;
 
    for (i = 0; i < irq_count; i++) {
        struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intids[i]);
        if (!irq)
            continue;
        update_lpi_config(kvm, irq, vcpu, false);
        vgic_put_irq(kvm, irq);
    }
 
    kfree(intids);
 
    if (vcpu->arch.vgic_cpu.vgic_v3.its_vpe.its_vm)
        its_invall_vpe(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe);
 
    return 0;
}

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vgic_its_resolve_lpi()

int vgic_its_resolve_lpi	(	struct kvm *	kvm,
		struct vgic_its *	its,
		u32	devid,
		u32	eventid,
		struct vgic_irq **	irq
	)

Definition at line 682 of file vgic-its.c.

{
    struct kvm_vcpu *vcpu;
    struct its_ite *ite;
 
    if (!its->enabled)
        return -EBUSY;
 
    ite = find_ite(its, devid, eventid);
    if (!ite || !its_is_collection_mapped(ite->collection))
        return E_ITS_INT_UNMAPPED_INTERRUPT;
 
    vcpu = collection_to_vcpu(kvm, ite->collection);
    if (!vcpu)
        return E_ITS_INT_UNMAPPED_INTERRUPT;
 
    if (!vgic_lpis_enabled(vcpu))
        return -EBUSY;
 
    vgic_its_cache_translation(kvm, its, devid, eventid, ite->irq);
 
    *irq = ite->irq;
    return 0;
}

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vgic_kick_vcpus()

void vgic_kick_vcpus

(

struct kvm *

kvm

)

Definition at line 1005 of file vgic.c.

{
    struct kvm_vcpu *vcpu;
    unsigned long c;
 
    /*
     * We've injected an interrupt, time to find out who deserves
     * a good kick...
     */
    kvm_for_each_vcpu(c, vcpu, kvm) {
        if (kvm_vgic_vcpu_pending_irq(vcpu)) {
            kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
            kvm_vcpu_kick(vcpu);
        }
    }
}

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vgic_lazy_init()

int vgic_lazy_init

(

struct kvm *

kvm

)

vgic_lazy_init: Lazy init is only allowed if the GIC exposed to the guest is a GICv2. A GICv3 must be explicitly initialized by userspace using the KVM_DEV_ARM_VGIC_GRP_CTRL KVM_DEVICE group. @kvm: kvm struct pointer

Definition at line 423 of file vgic-init.c.

{
    int ret = 0;
 
    if (unlikely(!vgic_initialized(kvm))) {
        /*
         * We only provide the automatic initialization of the VGIC
         * for the legacy case of a GICv2. Any other type must
         * be explicitly initialized once setup with the respective
         * KVM device call.
         */
        if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2)
            return -EBUSY;
 
        mutex_lock(&kvm->arch.config_lock);
        ret = vgic_init(kvm);
        mutex_unlock(&kvm->arch.config_lock);
    }
 
    return ret;
}

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vgic_lpi_translation_cache_destroy()

void vgic_lpi_translation_cache_destroy

(

struct kvm *

kvm

)

Definition at line 1927 of file vgic-its.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    struct vgic_translation_cache_entry *cte, *tmp;
 
    vgic_its_invalidate_cache(kvm);
 
    list_for_each_entry_safe(cte, tmp,
                 &dist->lpi_translation_cache, entry) {
        list_del(&cte->entry);
        kfree(cte);
    }
}

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vgic_lpi_translation_cache_init()

void vgic_lpi_translation_cache_init

(

struct kvm *

kvm

)

Definition at line 1903 of file vgic-its.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    unsigned int sz;
    int i;
 
    if (!list_empty(&dist->lpi_translation_cache))
        return;
 
    sz = atomic_read(&kvm->online_vcpus) * LPI_DEFAULT_PCPU_CACHE_SIZE;
 
    for (i = 0; i < sz; i++) {
        struct vgic_translation_cache_entry *cte;
 
        /* An allocation failure is not fatal */
        cte = kzalloc(sizeof(*cte), GFP_KERNEL_ACCOUNT);
        if (WARN_ON(!cte))
            break;
 
        INIT_LIST_HEAD(&cte->entry);
        list_add(&cte->entry, &dist->lpi_translation_cache);
    }
}

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vgic_lpis_enabled()

bool vgic_lpis_enabled

(

struct kvm_vcpu *

vcpu

)

Definition at line 238 of file vgic-mmio-v3.c.

{
    struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 
    return atomic_read(&vgic_cpu->ctlr) == GICR_CTLR_ENABLE_LPIS;
}

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vgic_msi_to_its()

struct vgic_its* vgic_msi_to_its	(	struct kvm *	kvm,
		struct kvm_msi *	msi
	)

Definition at line 708 of file vgic-its.c.

{
    u64 address;
    struct kvm_io_device *kvm_io_dev;
    struct vgic_io_device *iodev;
 
    if (!vgic_has_its(kvm))
        return ERR_PTR(-ENODEV);
 
    if (!(msi->flags & KVM_MSI_VALID_DEVID))
        return ERR_PTR(-EINVAL);
 
    address = (u64)msi->address_hi << 32 | msi->address_lo;
 
    kvm_io_dev = kvm_io_bus_get_dev(kvm, KVM_MMIO_BUS, address);
    if (!kvm_io_dev)
        return ERR_PTR(-EINVAL);
 
    if (kvm_io_dev->ops != &kvm_io_gic_ops)
        return ERR_PTR(-EINVAL);
 
    iodev = container_of(kvm_io_dev, struct vgic_io_device, dev);
    if (iodev->iodev_type != IODEV_ITS)
        return ERR_PTR(-EINVAL);
 
    return iodev->its;
}

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vgic_put_irq()

void vgic_put_irq	(	struct kvm *	kvm,
		struct vgic_irq *	irq
	)

Definition at line 139 of file vgic.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    unsigned long flags;
 
    if (irq->intid < VGIC_MIN_LPI)
        return;
 
    raw_spin_lock_irqsave(&dist->lpi_list_lock, flags);
    __vgic_put_lpi_locked(kvm, irq);
    raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
}

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vgic_queue_irq_unlock()

bool vgic_queue_irq_unlock	(	struct kvm *	kvm,
		struct vgic_irq *	irq,
		unsigned long	flags
	)

Definition at line 336 of file vgic.c.

{
    struct kvm_vcpu *vcpu;
 
    lockdep_assert_held(&irq->irq_lock);
 
retry:
    vcpu = vgic_target_oracle(irq);
    if (irq->vcpu || !vcpu) {
        /*
         * If this IRQ is already on a VCPU's ap_list, then it
         * cannot be moved or modified and there is no more work for
         * us to do.
         *
         * Otherwise, if the irq is not pending and enabled, it does
         * not need to be inserted into an ap_list and there is also
         * no more work for us to do.
         */
        raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 
        /*
         * We have to kick the VCPU here, because we could be
         * queueing an edge-triggered interrupt for which we
         * get no EOI maintenance interrupt. In that case,
         * while the IRQ is already on the VCPU's AP list, the
         * VCPU could have EOI'ed the original interrupt and
         * won't see this one until it exits for some other
         * reason.
         */
        if (vcpu) {
            kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
            kvm_vcpu_kick(vcpu);
        }
        return false;
    }
 
    /*
     * We must unlock the irq lock to take the ap_list_lock where
     * we are going to insert this new pending interrupt.
     */
    raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 
    /* someone can do stuff here, which we re-check below */
 
    raw_spin_lock_irqsave(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
    raw_spin_lock(&irq->irq_lock);
 
    /*
     * Did something change behind our backs?
     *
     * There are two cases:
     * 1) The irq lost its pending state or was disabled behind our
     *    backs and/or it was queued to another VCPU's ap_list.
     * 2) Someone changed the affinity on this irq behind our
     *    backs and we are now holding the wrong ap_list_lock.
     *
     * In both cases, drop the locks and retry.
     */
 
    if (unlikely(irq->vcpu || vcpu != vgic_target_oracle(irq))) {
        raw_spin_unlock(&irq->irq_lock);
        raw_spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock,
                       flags);
 
        raw_spin_lock_irqsave(&irq->irq_lock, flags);
        goto retry;
    }
 
    /*
     * Grab a reference to the irq to reflect the fact that it is
     * now in the ap_list.
     */
    vgic_get_irq_kref(irq);
    list_add_tail(&irq->ap_list, &vcpu->arch.vgic_cpu.ap_list_head);
    irq->vcpu = vcpu;
 
    raw_spin_unlock(&irq->irq_lock);
    raw_spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock, flags);
 
    kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
    kvm_vcpu_kick(vcpu);
 
    return true;
}

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vgic_register_dist_iodev()

int vgic_register_dist_iodev	(	struct kvm *	kvm,
		gpa_t	dist_base_address,
		enum	vgic_type
	)

Definition at line 1080 of file vgic-mmio.c.

{
    struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
    unsigned int len;
 
    switch (type) {
    case VGIC_V2:
        len = vgic_v2_init_dist_iodev(io_device);
        break;
    case VGIC_V3:
        len = vgic_v3_init_dist_iodev(io_device);
        break;
    default:
        BUG_ON(1);
    }
 
    io_device->base_addr = dist_base_address;
    io_device->iodev_type = IODEV_DIST;
    io_device->redist_vcpu = NULL;
 
    return kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
                       len, &io_device->dev);
}

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vgic_register_redist_iodev()

int vgic_register_redist_iodev

(

struct kvm_vcpu *

vcpu

)

vgic_register_redist_iodev - register a single redist iodev @vcpu: The VCPU to which the redistributor belongs

Register a KVM iodev for this VCPU's redistributor using the address provided.

Return 0 on success, -ERRNO otherwise.

Definition at line 746 of file vgic-mmio-v3.c.

{
    struct kvm *kvm = vcpu->kvm;
    struct vgic_dist *vgic = &kvm->arch.vgic;
    struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
    struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
    struct vgic_redist_region *rdreg;
    gpa_t rd_base;
    int ret = 0;
 
    lockdep_assert_held(&kvm->slots_lock);
    mutex_lock(&kvm->arch.config_lock);
 
    if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
        goto out_unlock;
 
    /*
     * We may be creating VCPUs before having set the base address for the
     * redistributor region, in which case we will come back to this
     * function for all VCPUs when the base address is set.  Just return
     * without doing any work for now.
     */
    rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
    if (!rdreg)
        goto out_unlock;
 
    if (!vgic_v3_check_base(kvm)) {
        ret = -EINVAL;
        goto out_unlock;
    }
 
    vgic_cpu->rdreg = rdreg;
    vgic_cpu->rdreg_index = rdreg->free_index;
 
    rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
 
    kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
    rd_dev->base_addr = rd_base;
    rd_dev->iodev_type = IODEV_REDIST;
    rd_dev->regions = vgic_v3_rd_registers;
    rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
    rd_dev->redist_vcpu = vcpu;
 
    mutex_unlock(&kvm->arch.config_lock);
 
    ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
                      2 * SZ_64K, &rd_dev->dev);
    if (ret)
        return ret;
 
    /* Protected by slots_lock */
    rdreg->free_index++;
    return 0;
 
out_unlock:
    mutex_unlock(&kvm->arch.config_lock);
    return ret;
}

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vgic_set_vmcr()

void vgic_set_vmcr	(	struct kvm_vcpu *	vcpu,
		struct vgic_vmcr *	vmcr
	)

Definition at line 843 of file vgic-mmio.c.

{
    if (kvm_vgic_global_state.type == VGIC_V2)
        vgic_v2_set_vmcr(vcpu, vmcr);
    else
        vgic_v3_set_vmcr(vcpu, vmcr);
}

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vgic_supports_direct_msis()

bool vgic_supports_direct_msis

(

struct kvm *

kvm

)

Definition at line 51 of file vgic-mmio-v3.c.

{
    return (kvm_vgic_global_state.has_gicv4_1 ||
        (kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm)));
}

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vgic_unregister_redist_iodev()

void vgic_unregister_redist_iodev

(

struct kvm_vcpu *

vcpu

)

Definition at line 805 of file vgic-mmio-v3.c.

{
    struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 
    kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
}

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vgic_v2_clear_lr()

void vgic_v2_clear_lr	(	struct kvm_vcpu *	vcpu,
		int	lr
	)

Definition at line 200 of file vgic-v2.c.

{
    vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
}

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vgic_v2_cpuif_uaccess()

int vgic_v2_cpuif_uaccess	(	struct kvm_vcpu *	vcpu,
		bool	is_write,
		int	offset,
		u32 *	val
	)

Definition at line 539 of file vgic-mmio-v2.c.

{
    struct vgic_io_device dev = {
        .regions = vgic_v2_cpu_registers,
        .nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
        .iodev_type = IODEV_CPUIF,
    };
 
    return vgic_uaccess(vcpu, &dev, is_write, offset, val);
}

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vgic_v2_dist_uaccess()

int vgic_v2_dist_uaccess	(	struct kvm_vcpu *	vcpu,
		bool	is_write,
		int	offset,
		u32 *	val
	)

Definition at line 551 of file vgic-mmio-v2.c.

{
    struct vgic_io_device dev = {
        .regions = vgic_v2_dist_registers,
        .nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
        .iodev_type = IODEV_DIST,
    };
 
    return vgic_uaccess(vcpu, &dev, is_write, offset, val);
}

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vgic_v2_enable()

void vgic_v2_enable

(

struct kvm_vcpu *

vcpu

)

Definition at line 260 of file vgic-v2.c.

{
    /*
     * By forcing VMCR to zero, the GIC will restore the binary
     * points to their reset values. Anything else resets to zero
     * anyway.
     */
    vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 
    /* Get the show on the road... */
    vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
}

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vgic_v2_fold_lr_state()

void vgic_v2_fold_lr_state

(

struct kvm_vcpu *

vcpu

)

Definition at line 49 of file vgic-v2.c.

{
    struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
    struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
    int lr;
 
    DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
 
    cpuif->vgic_hcr &= ~GICH_HCR_UIE;
 
    for (lr = 0; lr < vgic_cpu->vgic_v2.used_lrs; lr++) {
        u32 val = cpuif->vgic_lr[lr];
        u32 cpuid, intid = val & GICH_LR_VIRTUALID;
        struct vgic_irq *irq;
        bool deactivated;
 
        /* Extract the source vCPU id from the LR */
        cpuid = val & GICH_LR_PHYSID_CPUID;
        cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
        cpuid &= 7;
 
        /* Notify fds when the guest EOI'ed a level-triggered SPI */
        if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
            kvm_notify_acked_irq(vcpu->kvm, 0,
                         intid - VGIC_NR_PRIVATE_IRQS);
 
        irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
 
        raw_spin_lock(&irq->irq_lock);
 
        /* Always preserve the active bit, note deactivation */
        deactivated = irq->active && !(val & GICH_LR_ACTIVE_BIT);
        irq->active = !!(val & GICH_LR_ACTIVE_BIT);
 
        if (irq->active && vgic_irq_is_sgi(intid))
            irq->active_source = cpuid;
 
        /* Edge is the only case where we preserve the pending bit */
        if (irq->config == VGIC_CONFIG_EDGE &&
            (val & GICH_LR_PENDING_BIT)) {
            irq->pending_latch = true;
 
            if (vgic_irq_is_sgi(intid))
                irq->source |= (1 << cpuid);
        }
 
        /*
         * Clear soft pending state when level irqs have been acked.
         */
        if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))
            irq->pending_latch = false;
 
        /* Handle resampling for mapped interrupts if required */
        vgic_irq_handle_resampling(irq, deactivated, val & GICH_LR_PENDING_BIT);
 
        raw_spin_unlock(&irq->irq_lock);
        vgic_put_irq(vcpu->kvm, irq);
    }
 
    cpuif->used_lrs = 0;
}

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vgic_v2_get_vmcr()

void vgic_v2_get_vmcr	(	struct kvm_vcpu *	vcpu,
		struct vgic_vmcr *	vmcr
	)

Definition at line 232 of file vgic-v2.c.

{
    struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
    u32 vmcr;
 
    vmcr = cpu_if->vgic_vmcr;
 
    vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
        GICH_VMCR_ENABLE_GRP0_SHIFT;
    vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
        GICH_VMCR_ENABLE_GRP1_SHIFT;
    vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
        GICH_VMCR_ACK_CTL_SHIFT;
    vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
        GICH_VMCR_FIQ_EN_SHIFT;
    vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
        GICH_VMCR_CBPR_SHIFT;
    vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
        GICH_VMCR_EOI_MODE_SHIFT;
 
    vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
            GICH_VMCR_ALIAS_BINPOINT_SHIFT;
    vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
            GICH_VMCR_BINPOINT_SHIFT;
    vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
            GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
}

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vgic_v2_has_attr_regs()

int vgic_v2_has_attr_regs	(	struct kvm_device *	dev,
		struct kvm_device_attr *	attr
	)

Definition at line 497 of file vgic-mmio-v2.c.

{
    const struct vgic_register_region *region;
    struct vgic_io_device iodev;
    struct vgic_reg_attr reg_attr;
    struct kvm_vcpu *vcpu;
    gpa_t addr;
    int ret;
 
    ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
    if (ret)
        return ret;
 
    vcpu = reg_attr.vcpu;
    addr = reg_attr.addr;
 
    switch (attr->group) {
    case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
        iodev.regions = vgic_v2_dist_registers;
        iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
        iodev.base_addr = 0;
        break;
    case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
        iodev.regions = vgic_v2_cpu_registers;
        iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
        iodev.base_addr = 0;
        break;
    default:
        return -ENXIO;
    }
 
    /* We only support aligned 32-bit accesses. */
    if (addr & 3)
        return -ENXIO;
 
    region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
    if (!region)
        return -ENXIO;
 
    return 0;
}

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vgic_v2_init_lrs()

void vgic_v2_init_lrs

(

void

)

Definition at line 21 of file vgic-v2.c.

{
    int i;
 
    for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
        vgic_v2_write_lr(i, 0);
}

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vgic_v2_load()

void vgic_v2_load

(

struct kvm_vcpu *

vcpu

)

Definition at line 457 of file vgic-v2.c.

{
    struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 
    writel_relaxed(cpu_if->vgic_vmcr,
               kvm_vgic_global_state.vctrl_base + GICH_VMCR);
    writel_relaxed(cpu_if->vgic_apr,
               kvm_vgic_global_state.vctrl_base + GICH_APR);
}

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vgic_v2_map_resources()

int vgic_v2_map_resources

(

struct kvm *

kvm

)

Definition at line 289 of file vgic-v2.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    int ret = 0;
 
    if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
        IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
        kvm_debug("Need to set vgic cpu and dist addresses first\n");
        return -ENXIO;
    }
 
    if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
        kvm_debug("VGIC CPU and dist frames overlap\n");
        return -EINVAL;
    }
 
    /*
     * Initialize the vgic if this hasn't already been done on demand by
     * accessing the vgic state from userspace.
     */
    ret = vgic_init(kvm);
    if (ret) {
        kvm_err("Unable to initialize VGIC dynamic data structures\n");
        return ret;
    }
 
    if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
        ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
                        kvm_vgic_global_state.vcpu_base,
                        KVM_VGIC_V2_CPU_SIZE, true);
        if (ret) {
            kvm_err("Unable to remap VGIC CPU to VCPU\n");
            return ret;
        }
    }
 
    return 0;
}

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vgic_v2_parse_attr()

int vgic_v2_parse_attr	(	struct kvm_device *	dev,
		struct kvm_device_attr *	attr,
		struct vgic_reg_attr *	reg_attr
	)

Definition at line 338 of file vgic-kvm-device.c.

{
    int cpuid;
 
    cpuid = FIELD_GET(KVM_DEV_ARM_VGIC_CPUID_MASK, attr->attr);
 
    reg_attr->vcpu = kvm_get_vcpu_by_id(dev->kvm, cpuid);
    reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
 
    return 0;
}

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vgic_v2_populate_lr()

void vgic_v2_populate_lr	(	struct kvm_vcpu *	vcpu,
		struct vgic_irq *	irq,
		int	lr
	)

Definition at line 122 of file vgic-v2.c.

{
    u32 val = irq->intid;
    bool allow_pending = true;
 
    if (irq->active) {
        val |= GICH_LR_ACTIVE_BIT;
        if (vgic_irq_is_sgi(irq->intid))
            val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
        if (vgic_irq_is_multi_sgi(irq)) {
            allow_pending = false;
            val |= GICH_LR_EOI;
        }
    }
 
    if (irq->group)
        val |= GICH_LR_GROUP1;
 
    if (irq->hw && !vgic_irq_needs_resampling(irq)) {
        val |= GICH_LR_HW;
        val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
        /*
         * Never set pending+active on a HW interrupt, as the
         * pending state is kept at the physical distributor
         * level.
         */
        if (irq->active)
            allow_pending = false;
    } else {
        if (irq->config == VGIC_CONFIG_LEVEL) {
            val |= GICH_LR_EOI;
 
            /*
             * Software resampling doesn't work very well
             * if we allow P+A, so let's not do that.
             */
            if (irq->active)
                allow_pending = false;
        }
    }
 
    if (allow_pending && irq_is_pending(irq)) {
        val |= GICH_LR_PENDING_BIT;
 
        if (irq->config == VGIC_CONFIG_EDGE)
            irq->pending_latch = false;
 
        if (vgic_irq_is_sgi(irq->intid)) {
            u32 src = ffs(irq->source);
 
            if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
                       irq->intid))
                return;
 
            val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
            irq->source &= ~(1 << (src - 1));
            if (irq->source) {
                irq->pending_latch = true;
                val |= GICH_LR_EOI;
            }
        }
    }
 
    /*
     * Level-triggered mapped IRQs are special because we only observe
     * rising edges as input to the VGIC.  We therefore lower the line
     * level here, so that we can take new virtual IRQs.  See
     * vgic_v2_fold_lr_state for more info.
     */
    if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
        irq->line_level = false;
 
    /* The GICv2 LR only holds five bits of priority. */
    val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
 
    vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
}

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vgic_v2_probe()

int vgic_v2_probe

(

const struct gic_kvm_info *

info

)

vgic_v2_probe - probe for a VGICv2 compatible interrupt controller @info: pointer to the GIC description

Returns 0 if the VGICv2 has been probed successfully, returns an error code otherwise

Definition at line 337 of file vgic-v2.c.

{
    int ret;
    u32 vtr;
 
    if (is_protected_kvm_enabled()) {
        kvm_err("GICv2 not supported in protected mode\n");
        return -ENXIO;
    }
 
    if (!info->vctrl.start) {
        kvm_err("GICH not present in the firmware table\n");
        return -ENXIO;
    }
 
    if (!PAGE_ALIGNED(info->vcpu.start) ||
        !PAGE_ALIGNED(resource_size(&info->vcpu))) {
        kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
 
        ret = create_hyp_io_mappings(info->vcpu.start,
                         resource_size(&info->vcpu),
                         &kvm_vgic_global_state.vcpu_base_va,
                         &kvm_vgic_global_state.vcpu_hyp_va);
        if (ret) {
            kvm_err("Cannot map GICV into hyp\n");
            goto out;
        }
 
        static_branch_enable(&vgic_v2_cpuif_trap);
    }
 
    ret = create_hyp_io_mappings(info->vctrl.start,
                     resource_size(&info->vctrl),
                     &kvm_vgic_global_state.vctrl_base,
                     &kvm_vgic_global_state.vctrl_hyp);
    if (ret) {
        kvm_err("Cannot map VCTRL into hyp\n");
        goto out;
    }
 
    vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
    kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
 
    ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
    if (ret) {
        kvm_err("Cannot register GICv2 KVM device\n");
        goto out;
    }
 
    kvm_vgic_global_state.can_emulate_gicv2 = true;
    kvm_vgic_global_state.vcpu_base = info->vcpu.start;
    kvm_vgic_global_state.type = VGIC_V2;
    kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
 
    kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
 
    return 0;
out:
    if (kvm_vgic_global_state.vctrl_base)
        iounmap(kvm_vgic_global_state.vctrl_base);
    if (kvm_vgic_global_state.vcpu_base_va)
        iounmap(kvm_vgic_global_state.vcpu_base_va);
 
    return ret;
}

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vgic_v2_put()

void vgic_v2_put

(

struct kvm_vcpu *

vcpu

)

Definition at line 474 of file vgic-v2.c.

{
    struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 
    vgic_v2_vmcr_sync(vcpu);
    cpu_if->vgic_apr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_APR);
}

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vgic_v2_restore_state()

void vgic_v2_restore_state

(

struct kvm_vcpu *

vcpu

)

Definition at line 438 of file vgic-v2.c.

{
    struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
    void __iomem *base = kvm_vgic_global_state.vctrl_base;
    u64 used_lrs = cpu_if->used_lrs;
    int i;
 
    if (!base)
        return;
 
    if (used_lrs) {
        writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
        for (i = 0; i < used_lrs; i++) {
            writel_relaxed(cpu_if->vgic_lr[i],
                       base + GICH_LR0 + (i * 4));
        }
    }
}

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vgic_v2_save_state()

void vgic_v2_save_state

(

struct kvm_vcpu *

vcpu

)

Definition at line 424 of file vgic-v2.c.

{
    void __iomem *base = kvm_vgic_global_state.vctrl_base;
    u64 used_lrs = vcpu->arch.vgic_cpu.vgic_v2.used_lrs;
 
    if (!base)
        return;
 
    if (used_lrs) {
        save_lrs(vcpu, base);
        writel_relaxed(0, base + GICH_HCR);
    }
}

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vgic_v2_set_underflow()

void vgic_v2_set_underflow

(

struct kvm_vcpu *

vcpu

)

Definition at line 29 of file vgic-v2.c.

{
    struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
 
    cpuif->vgic_hcr |= GICH_HCR_UIE;
}

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vgic_v2_set_vmcr()

void vgic_v2_set_vmcr	(	struct kvm_vcpu *	vcpu,
		struct vgic_vmcr *	vmcr
	)

Definition at line 205 of file vgic-v2.c.

{
    struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
    u32 vmcr;
 
    vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
        GICH_VMCR_ENABLE_GRP0_MASK;
    vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
        GICH_VMCR_ENABLE_GRP1_MASK;
    vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
        GICH_VMCR_ACK_CTL_MASK;
    vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
        GICH_VMCR_FIQ_EN_MASK;
    vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
        GICH_VMCR_CBPR_MASK;
    vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
        GICH_VMCR_EOI_MODE_MASK;
    vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
        GICH_VMCR_ALIAS_BINPOINT_MASK;
    vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
        GICH_VMCR_BINPOINT_MASK;
    vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
         GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
 
    cpu_if->vgic_vmcr = vmcr;
}

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vgic_v2_vmcr_sync()

void vgic_v2_vmcr_sync

(

struct kvm_vcpu *

vcpu

)

Definition at line 467 of file vgic-v2.c.

{
    struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 
    cpu_if->vgic_vmcr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VMCR);
}

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vgic_v3_check_base()

bool vgic_v3_check_base

(

struct kvm *

kvm

)

Definition at line 477 of file vgic-v3.c.

{
    struct vgic_dist *d = &kvm->arch.vgic;
    struct vgic_redist_region *rdreg;
 
    if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
        d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
        return false;
 
    list_for_each_entry(rdreg, &d->rd_regions, list) {
        size_t sz = vgic_v3_rd_region_size(kvm, rdreg);
 
        if (vgic_check_iorange(kvm, VGIC_ADDR_UNDEF,
                       rdreg->base, SZ_64K, sz))
            return false;
    }
 
    if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base))
        return true;
 
    return !vgic_v3_rdist_overlap(kvm, d->vgic_dist_base,
                      KVM_VGIC_V3_DIST_SIZE);
}

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vgic_v3_clear_lr()

void vgic_v3_clear_lr	(	struct kvm_vcpu *	vcpu,
		int	lr
	)

Definition at line 189 of file vgic-v3.c.

{
    vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
}

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vgic_v3_cpu_sysregs_uaccess()

int vgic_v3_cpu_sysregs_uaccess	(	struct kvm_vcpu *	vcpu,
		struct kvm_device_attr *	attr,
		bool	is_write
	)

Definition at line 351 of file vgic-sys-reg-v3.c.

{
    struct kvm_one_reg reg = {
        .id = attr_to_id(attr->attr),
        .addr   = attr->addr,
    };
 
    if (is_write)
        return kvm_sys_reg_set_user(vcpu, &reg, gic_v3_icc_reg_descs,
                        ARRAY_SIZE(gic_v3_icc_reg_descs));
    else
        return kvm_sys_reg_get_user(vcpu, &reg, gic_v3_icc_reg_descs,
                        ARRAY_SIZE(gic_v3_icc_reg_descs));
}

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vgic_v3_dist_uaccess()

int vgic_v3_dist_uaccess	(	struct kvm_vcpu *	vcpu,
		bool	is_write,
		int	offset,
		u32 *	val
	)

Definition at line 1095 of file vgic-mmio-v3.c.

{
    struct vgic_io_device dev = {
        .regions = vgic_v3_dist_registers,
        .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
    };
 
    return vgic_uaccess(vcpu, &dev, is_write, offset, val);
}

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vgic_v3_enable()

void vgic_v3_enable

(

struct kvm_vcpu *

vcpu

)

Definition at line 260 of file vgic-v3.c.

{
    struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 
    /*
     * By forcing VMCR to zero, the GIC will restore the binary
     * points to their reset values. Anything else resets to zero
     * anyway.
     */
    vgic_v3->vgic_vmcr = 0;
 
    /*
     * If we are emulating a GICv3, we do it in an non-GICv2-compatible
     * way, so we force SRE to 1 to demonstrate this to the guest.
     * Also, we don't support any form of IRQ/FIQ bypass.
     * This goes with the spec allowing the value to be RAO/WI.
     */
    if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
        vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
                     ICC_SRE_EL1_DFB |
                     ICC_SRE_EL1_SRE);
        vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
    } else {
        vgic_v3->vgic_sre = 0;
    }
 
    vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
                       ICH_VTR_ID_BITS_MASK) >>
                       ICH_VTR_ID_BITS_SHIFT;
    vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
                        ICH_VTR_PRI_BITS_MASK) >>
                        ICH_VTR_PRI_BITS_SHIFT) + 1;
 
    /* Get the show on the road... */
    vgic_v3->vgic_hcr = ICH_HCR_EN;
    if (group0_trap)
        vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
    if (group1_trap)
        vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
    if (common_trap)
        vgic_v3->vgic_hcr |= ICH_HCR_TC;
    if (dir_trap)
        vgic_v3->vgic_hcr |= ICH_HCR_TDIR;
}

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vgic_v3_fold_lr_state()

void vgic_v3_fold_lr_state

(

struct kvm_vcpu *

vcpu

)

Definition at line 35 of file vgic-v3.c.

{
    struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
    struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
    u32 model = vcpu->kvm->arch.vgic.vgic_model;
    int lr;
 
    DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
 
    cpuif->vgic_hcr &= ~ICH_HCR_UIE;
 
    for (lr = 0; lr < cpuif->used_lrs; lr++) {
        u64 val = cpuif->vgic_lr[lr];
        u32 intid, cpuid;
        struct vgic_irq *irq;
        bool is_v2_sgi = false;
        bool deactivated;
 
        cpuid = val & GICH_LR_PHYSID_CPUID;
        cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
 
        if (model == KVM_DEV_TYPE_ARM_VGIC_V3) {
            intid = val & ICH_LR_VIRTUAL_ID_MASK;
        } else {
            intid = val & GICH_LR_VIRTUALID;
            is_v2_sgi = vgic_irq_is_sgi(intid);
        }
 
        /* Notify fds when the guest EOI'ed a level-triggered IRQ */
        if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
            kvm_notify_acked_irq(vcpu->kvm, 0,
                         intid - VGIC_NR_PRIVATE_IRQS);
 
        irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
        if (!irq)   /* An LPI could have been unmapped. */
            continue;
 
        raw_spin_lock(&irq->irq_lock);
 
        /* Always preserve the active bit, note deactivation */
        deactivated = irq->active && !(val & ICH_LR_ACTIVE_BIT);
        irq->active = !!(val & ICH_LR_ACTIVE_BIT);
 
        if (irq->active && is_v2_sgi)
            irq->active_source = cpuid;
 
        /* Edge is the only case where we preserve the pending bit */
        if (irq->config == VGIC_CONFIG_EDGE &&
            (val & ICH_LR_PENDING_BIT)) {
            irq->pending_latch = true;
 
            if (is_v2_sgi)
                irq->source |= (1 << cpuid);
        }
 
        /*
         * Clear soft pending state when level irqs have been acked.
         */
        if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE))
            irq->pending_latch = false;
 
        /* Handle resampling for mapped interrupts if required */
        vgic_irq_handle_resampling(irq, deactivated, val & ICH_LR_PENDING_BIT);
 
        raw_spin_unlock(&irq->irq_lock);
        vgic_put_irq(vcpu->kvm, irq);
    }
 
    cpuif->used_lrs = 0;
}

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vgic_v3_free_redist_region()

void vgic_v3_free_redist_region

(

struct vgic_redist_region *

rdreg

)

Definition at line 922 of file vgic-mmio-v3.c.

{
    list_del(&rdreg->list);
    kfree(rdreg);
}

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vgic_v3_get_vmcr()

void vgic_v3_get_vmcr	(	struct kvm_vcpu *	vcpu,
		struct vgic_vmcr *	vmcr
	)

Definition at line 224 of file vgic-v3.c.

{
    struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
    u32 model = vcpu->kvm->arch.vgic.vgic_model;
    u32 vmcr;
 
    vmcr = cpu_if->vgic_vmcr;
 
    if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
        vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
            ICH_VMCR_ACK_CTL_SHIFT;
        vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
            ICH_VMCR_FIQ_EN_SHIFT;
    } else {
        /*
         * When emulating GICv3 on GICv3 with SRE=1 on the
         * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
         */
        vmcrp->fiqen = 1;
        vmcrp->ackctl = 0;
    }
 
    vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
    vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
    vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
    vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
    vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
    vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
    vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
}

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vgic_v3_has_attr_regs()

int vgic_v3_has_attr_regs	(	struct kvm_device *	dev,
		struct kvm_device_attr *	attr
	)

Definition at line 956 of file vgic-mmio-v3.c.

{
    const struct vgic_register_region *region;
    struct vgic_io_device iodev;
    struct vgic_reg_attr reg_attr;
    struct kvm_vcpu *vcpu;
    gpa_t addr;
    int ret;
 
    ret = vgic_v3_parse_attr(dev, attr, &reg_attr);
    if (ret)
        return ret;
 
    vcpu = reg_attr.vcpu;
    addr = reg_attr.addr;
 
    switch (attr->group) {
    case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
        iodev.regions = vgic_v3_dist_registers;
        iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
        iodev.base_addr = 0;
        break;
    case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
        iodev.regions = vgic_v3_rd_registers;
        iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
        iodev.base_addr = 0;
        break;
    }
    case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
        return vgic_v3_has_cpu_sysregs_attr(vcpu, attr);
    default:
        return -ENXIO;
    }
 
    /* We only support aligned 32-bit accesses. */
    if (addr & 3)
        return -ENXIO;
 
    region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
    if (!region)
        return -ENXIO;
 
    return 0;
}

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vgic_v3_has_cpu_sysregs_attr()

int vgic_v3_has_cpu_sysregs_attr	(	struct kvm_vcpu *	vcpu,
		struct kvm_device_attr *	attr
	)

Definition at line 342 of file vgic-sys-reg-v3.c.

{
    if (get_reg_by_id(attr_to_id(attr->attr), gic_v3_icc_reg_descs,
              ARRAY_SIZE(gic_v3_icc_reg_descs)))
        return 0;
 
    return -ENXIO;
}

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vgic_v3_line_level_info_uaccess()

int vgic_v3_line_level_info_uaccess	(	struct kvm_vcpu *	vcpu,
		bool	is_write,
		u32	intid,
		u32 *	val
	)

Definition at line 1117 of file vgic-mmio-v3.c.

{
    if (intid % 32)
        return -EINVAL;
 
    if (is_write)
        vgic_write_irq_line_level_info(vcpu, intid, *val);
    else
        *val = vgic_read_irq_line_level_info(vcpu, intid);
 
    return 0;
}

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vgic_v3_load()

void vgic_v3_load

(

struct kvm_vcpu *

vcpu

)

Definition at line 720 of file vgic-v3.c.

{
    struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 
    /*
     * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
     * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
     * VMCR_EL2 save/restore in the world switch.
     */
    if (likely(cpu_if->vgic_sre))
        kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
 
    kvm_call_hyp(__vgic_v3_restore_aprs, cpu_if);
 
    if (has_vhe())
        __vgic_v3_activate_traps(cpu_if);
 
    WARN_ON(vgic_v4_load(vcpu));
}

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vgic_v3_lpi_sync_pending_status()

int vgic_v3_lpi_sync_pending_status	(	struct kvm *	kvm,
		struct vgic_irq *	irq
	)

Definition at line 305 of file vgic-v3.c.

{
    struct kvm_vcpu *vcpu;
    int byte_offset, bit_nr;
    gpa_t pendbase, ptr;
    bool status;
    u8 val;
    int ret;
    unsigned long flags;
 
retry:
    vcpu = irq->target_vcpu;
    if (!vcpu)
        return 0;
 
    pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 
    byte_offset = irq->intid / BITS_PER_BYTE;
    bit_nr = irq->intid % BITS_PER_BYTE;
    ptr = pendbase + byte_offset;
 
    ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
    if (ret)
        return ret;
 
    status = val & (1 << bit_nr);
 
    raw_spin_lock_irqsave(&irq->irq_lock, flags);
    if (irq->target_vcpu != vcpu) {
        raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
        goto retry;
    }
    irq->pending_latch = status;
    vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 
    if (status) {
        /* clear consumed data */
        val &= ~(1 << bit_nr);
        ret = vgic_write_guest_lock(kvm, ptr, &val, 1);
        if (ret)
            return ret;
    }
    return 0;
}

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vgic_v3_map_resources()

int vgic_v3_map_resources

(

struct kvm *

kvm

)

Definition at line 538 of file vgic-v3.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    struct kvm_vcpu *vcpu;
    unsigned long c;
 
    kvm_for_each_vcpu(c, vcpu, kvm) {
        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 
        if (IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) {
            kvm_debug("vcpu %ld redistributor base not set\n", c);
            return -ENXIO;
        }
    }
 
    if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base)) {
        kvm_debug("Need to set vgic distributor addresses first\n");
        return -ENXIO;
    }
 
    if (!vgic_v3_check_base(kvm)) {
        kvm_debug("VGIC redist and dist frames overlap\n");
        return -EINVAL;
    }
 
    /*
     * For a VGICv3 we require the userland to explicitly initialize
     * the VGIC before we need to use it.
     */
    if (!vgic_initialized(kvm)) {
        return -EBUSY;
    }
 
    if (kvm_vgic_global_state.has_gicv4_1)
        vgic_v4_configure_vsgis(kvm);
 
    return 0;
}

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vgic_v3_max_apr_idx()

static int vgic_v3_max_apr_idx ( struct kvm_vcpu *  vcpu )

inlinestatic

Definition at line 275 of file vgic.h.

{
    struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
 
    /*
     * num_pri_bits are initialized with HW supported values.
     * We can rely safely on num_pri_bits even if VM has not
     * restored ICC_CTLR_EL1 before restoring APnR registers.
     */
    switch (cpu_if->num_pri_bits) {
    case 7: return 3;
    case 6: return 1;
    default: return 0;
    }
}

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vgic_v3_parse_attr()

int vgic_v3_parse_attr	(	struct kvm_device *	dev,
		struct kvm_device_attr *	attr,
		struct vgic_reg_attr *	reg_attr
	)

Definition at line 474 of file vgic-kvm-device.c.

{
    unsigned long vgic_mpidr, mpidr_reg;
 
    /*
     * For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group,
     * attr might not hold MPIDR. Hence assume vcpu0.
     */
    if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) {
        vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
                  KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;
 
        mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
        reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg);
    } else {
        reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0);
    }
 
    if (!reg_attr->vcpu)
        return -EINVAL;
 
    reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
 
    return 0;
}

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vgic_v3_populate_lr()

void vgic_v3_populate_lr	(	struct kvm_vcpu *	vcpu,
		struct vgic_irq *	irq,
		int	lr
	)

Definition at line 107 of file vgic-v3.c.

{
    u32 model = vcpu->kvm->arch.vgic.vgic_model;
    u64 val = irq->intid;
    bool allow_pending = true, is_v2_sgi;
 
    is_v2_sgi = (vgic_irq_is_sgi(irq->intid) &&
             model == KVM_DEV_TYPE_ARM_VGIC_V2);
 
    if (irq->active) {
        val |= ICH_LR_ACTIVE_BIT;
        if (is_v2_sgi)
            val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
        if (vgic_irq_is_multi_sgi(irq)) {
            allow_pending = false;
            val |= ICH_LR_EOI;
        }
    }
 
    if (irq->hw && !vgic_irq_needs_resampling(irq)) {
        val |= ICH_LR_HW;
        val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
        /*
         * Never set pending+active on a HW interrupt, as the
         * pending state is kept at the physical distributor
         * level.
         */
        if (irq->active)
            allow_pending = false;
    } else {
        if (irq->config == VGIC_CONFIG_LEVEL) {
            val |= ICH_LR_EOI;
 
            /*
             * Software resampling doesn't work very well
             * if we allow P+A, so let's not do that.
             */
            if (irq->active)
                allow_pending = false;
        }
    }
 
    if (allow_pending && irq_is_pending(irq)) {
        val |= ICH_LR_PENDING_BIT;
 
        if (irq->config == VGIC_CONFIG_EDGE)
            irq->pending_latch = false;
 
        if (vgic_irq_is_sgi(irq->intid) &&
            model == KVM_DEV_TYPE_ARM_VGIC_V2) {
            u32 src = ffs(irq->source);
 
            if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
                       irq->intid))
                return;
 
            val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
            irq->source &= ~(1 << (src - 1));
            if (irq->source) {
                irq->pending_latch = true;
                val |= ICH_LR_EOI;
            }
        }
    }
 
    /*
     * Level-triggered mapped IRQs are special because we only observe
     * rising edges as input to the VGIC.  We therefore lower the line
     * level here, so that we can take new virtual IRQs.  See
     * vgic_v3_fold_lr_state for more info.
     */
    if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT))
        irq->line_level = false;
 
    if (irq->group)
        val |= ICH_LR_GROUP;
 
    val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
 
    vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
}

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vgic_v3_probe()

int vgic_v3_probe

(

const struct gic_kvm_info *

info

)

vgic_v3_probe - probe for a VGICv3 compatible interrupt controller @info: pointer to the GIC description

Returns 0 if the VGICv3 has been probed successfully, returns an error code otherwise

Definition at line 632 of file vgic-v3.c.

{
    u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
    bool has_v2;
    int ret;
 
    has_v2 = ich_vtr_el2 >> 63;
    ich_vtr_el2 = (u32)ich_vtr_el2;
 
    /*
     * The ListRegs field is 5 bits, but there is an architectural
     * maximum of 16 list registers. Just ignore bit 4...
     */
    kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
    kvm_vgic_global_state.can_emulate_gicv2 = false;
    kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
 
    /* GICv4 support? */
    if (info->has_v4) {
        kvm_vgic_global_state.has_gicv4 = gicv4_enable;
        kvm_vgic_global_state.has_gicv4_1 = info->has_v4_1 && gicv4_enable;
        kvm_info("GICv4%s support %sabled\n",
             kvm_vgic_global_state.has_gicv4_1 ? ".1" : "",
             gicv4_enable ? "en" : "dis");
    }
 
    kvm_vgic_global_state.vcpu_base = 0;
 
    if (!info->vcpu.start) {
        kvm_info("GICv3: no GICV resource entry\n");
    } else if (!has_v2) {
        pr_warn(FW_BUG "CPU interface incapable of MMIO access\n");
    } else if (!PAGE_ALIGNED(info->vcpu.start)) {
        pr_warn("GICV physical address 0x%llx not page aligned\n",
            (unsigned long long)info->vcpu.start);
    } else if (kvm_get_mode() != KVM_MODE_PROTECTED) {
        kvm_vgic_global_state.vcpu_base = info->vcpu.start;
        kvm_vgic_global_state.can_emulate_gicv2 = true;
        ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
        if (ret) {
            kvm_err("Cannot register GICv2 KVM device.\n");
            return ret;
        }
        kvm_info("vgic-v2@%llx\n", info->vcpu.start);
    }
    ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
    if (ret) {
        kvm_err("Cannot register GICv3 KVM device.\n");
        kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
        return ret;
    }
 
    if (kvm_vgic_global_state.vcpu_base == 0)
        kvm_info("disabling GICv2 emulation\n");
 
    if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
        group0_trap = true;
        group1_trap = true;
    }
 
    if (vgic_v3_broken_seis()) {
        kvm_info("GICv3 with broken locally generated SEI\n");
 
        kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_SEIS_MASK;
        group0_trap = true;
        group1_trap = true;
        if (ich_vtr_el2 & ICH_VTR_TDS_MASK)
            dir_trap = true;
        else
            common_trap = true;
    }
 
    if (group0_trap || group1_trap || common_trap | dir_trap) {
        kvm_info("GICv3 sysreg trapping enabled ([%s%s%s%s], reduced performance)\n",
             group0_trap ? "G0" : "",
             group1_trap ? "G1" : "",
             common_trap ? "C"  : "",
             dir_trap    ? "D"  : "");
        static_branch_enable(&vgic_v3_cpuif_trap);
    }
 
    kvm_vgic_global_state.vctrl_base = NULL;
    kvm_vgic_global_state.type = VGIC_V3;
    kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
 
    return 0;
}

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vgic_v3_put()

void vgic_v3_put

(

struct kvm_vcpu *

vcpu

)

Definition at line 748 of file vgic-v3.c.

{
    struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 
    WARN_ON(vgic_v4_put(vcpu));
 
    vgic_v3_vmcr_sync(vcpu);
 
    kvm_call_hyp(__vgic_v3_save_aprs, cpu_if);
 
    if (has_vhe())
        __vgic_v3_deactivate_traps(cpu_if);
}

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vgic_v3_rd_region_size()

static size_t vgic_v3_rd_region_size ( struct kvm *  kvm, struct vgic_redist_region *  rdreg  )

inlinestatic

Definition at line 303 of file vgic.h.

{
    if (!rdreg->count)
        return atomic_read(&kvm->online_vcpus) * KVM_VGIC_V3_REDIST_SIZE;
    else
        return rdreg->count * KVM_VGIC_V3_REDIST_SIZE;
}

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vgic_v3_rdist_free_slot()

struct vgic_redist_region* vgic_v3_rdist_free_slot

(

struct list_head *

rd_regions

)

vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one which has free space to put a new rdist region.

@rd_regions: redistributor region list head

A redistributor regions maps n redistributors, n = region size / (2 x 64kB). Stride between redistributors is 0 and regions are filled in the index order.

Return: the redist region handle, if any, that has space to map a new rdist region.

Definition at line 513 of file vgic-v3.c.

{
    struct vgic_redist_region *rdreg;
 
    list_for_each_entry(rdreg, rd_regions, list) {
        if (!vgic_v3_redist_region_full(rdreg))
            return rdreg;
    }
    return NULL;
}

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vgic_v3_rdist_overlap()

bool vgic_v3_rdist_overlap	(	struct kvm *	kvm,
		gpa_t	base,
		size_t	size
	)

vgic_v3_rdist_overlap - check if a region overlaps with any existing redistributor region

@kvm: kvm handle @base: base of the region @size: size of region

Return: true if there is an overlap

Definition at line 460 of file vgic-v3.c.

{
    struct vgic_dist *d = &kvm->arch.vgic;
    struct vgic_redist_region *rdreg;
 
    list_for_each_entry(rdreg, &d->rd_regions, list) {
        if ((base + size > rdreg->base) &&
            (base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg)))
            return true;
    }
    return false;
}

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vgic_v3_rdist_region_from_index()

struct vgic_redist_region* vgic_v3_rdist_region_from_index	(	struct kvm *	kvm,
		u32	index
	)

Definition at line 524 of file vgic-v3.c.

{
    struct list_head *rd_regions = &kvm->arch.vgic.rd_regions;
    struct vgic_redist_region *rdreg;
 
    list_for_each_entry(rdreg, rd_regions, list) {
        if (rdreg->index == index)
            return rdreg;
    }
    return NULL;
}

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vgic_v3_redist_region_full()

static bool vgic_v3_redist_region_full ( struct vgic_redist_region *  region )

inlinestatic

Definition at line 292 of file vgic.h.

{
    if (!region->count)
        return false;
 
    return (region->free_index >= region->count);
}

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vgic_v3_redist_uaccess()

int vgic_v3_redist_uaccess	(	struct kvm_vcpu *	vcpu,
		bool	is_write,
		int	offset,
		u32 *	val
	)

Definition at line 1106 of file vgic-mmio-v3.c.

{
    struct vgic_io_device rd_dev = {
        .regions = vgic_v3_rd_registers,
        .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers),
    };
 
    return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
}

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vgic_v3_save_pending_tables()

int vgic_v3_save_pending_tables

(

struct kvm *

kvm

)

vgic_v3_save_pending_tables - Save the pending tables into guest RAM kvm lock and all vcpu lock must be held

Definition at line 377 of file vgic-v3.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    struct vgic_irq *irq;
    gpa_t last_ptr = ~(gpa_t)0;
    bool vlpi_avail = false;
    int ret = 0;
    u8 val;
 
    if (unlikely(!vgic_initialized(kvm)))
        return -ENXIO;
 
    /*
     * A preparation for getting any VLPI states.
     * The above vgic initialized check also ensures that the allocation
     * and enabling of the doorbells have already been done.
     */
    if (kvm_vgic_global_state.has_gicv4_1) {
        unmap_all_vpes(kvm);
        vlpi_avail = true;
    }
 
    list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
        int byte_offset, bit_nr;
        struct kvm_vcpu *vcpu;
        gpa_t pendbase, ptr;
        bool is_pending;
        bool stored;
 
        vcpu = irq->target_vcpu;
        if (!vcpu)
            continue;
 
        pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 
        byte_offset = irq->intid / BITS_PER_BYTE;
        bit_nr = irq->intid % BITS_PER_BYTE;
        ptr = pendbase + byte_offset;
 
        if (ptr != last_ptr) {
            ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
            if (ret)
                goto out;
            last_ptr = ptr;
        }
 
        stored = val & (1U << bit_nr);
 
        is_pending = irq->pending_latch;
 
        if (irq->hw && vlpi_avail)
            vgic_v4_get_vlpi_state(irq, &is_pending);
 
        if (stored == is_pending)
            continue;
 
        if (is_pending)
            val |= 1 << bit_nr;
        else
            val &= ~(1 << bit_nr);
 
        ret = vgic_write_guest_lock(kvm, ptr, &val, 1);
        if (ret)
            goto out;
    }
 
out:
    if (vlpi_avail)
        map_all_vpes(kvm);
 
    return ret;
}

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vgic_v3_set_redist_base()

int vgic_v3_set_redist_base	(	struct kvm *	kvm,
		u32	index,
		u64	addr,
		u32	count
	)

Definition at line 928 of file vgic-mmio-v3.c.

{
    int ret;
 
    mutex_lock(&kvm->arch.config_lock);
    ret = vgic_v3_alloc_redist_region(kvm, index, addr, count);
    mutex_unlock(&kvm->arch.config_lock);
    if (ret)
        return ret;
 
    /*
     * Register iodevs for each existing VCPU.  Adding more VCPUs
     * afterwards will register the iodevs when needed.
     */
    ret = vgic_register_all_redist_iodevs(kvm);
    if (ret) {
        struct vgic_redist_region *rdreg;
 
        mutex_lock(&kvm->arch.config_lock);
        rdreg = vgic_v3_rdist_region_from_index(kvm, index);
        vgic_v3_free_redist_region(rdreg);
        mutex_unlock(&kvm->arch.config_lock);
        return ret;
    }
 
    return 0;
}

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vgic_v3_set_underflow()

void vgic_v3_set_underflow

(

struct kvm_vcpu *

vcpu

)

Definition at line 22 of file vgic-v3.c.

{
    struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
 
    cpuif->vgic_hcr |= ICH_HCR_UIE;
}

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vgic_v3_set_vmcr()

void vgic_v3_set_vmcr	(	struct kvm_vcpu *	vcpu,
		struct vgic_vmcr *	vmcr
	)

Definition at line 194 of file vgic-v3.c.

{
    struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
    u32 model = vcpu->kvm->arch.vgic.vgic_model;
    u32 vmcr;
 
    if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
        vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
            ICH_VMCR_ACK_CTL_MASK;
        vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
            ICH_VMCR_FIQ_EN_MASK;
    } else {
        /*
         * When emulating GICv3 on GICv3 with SRE=1 on the
         * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
         */
        vmcr = ICH_VMCR_FIQ_EN_MASK;
    }
 
    vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
    vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
    vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
    vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
    vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
    vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
    vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
 
    cpu_if->vgic_vmcr = vmcr;
}

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vgic_v3_vmcr_sync()

void vgic_v3_vmcr_sync

(

struct kvm_vcpu *

vcpu

)

Definition at line 740 of file vgic-v3.c.

{
    struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 
    if (likely(cpu_if->vgic_sre))
        cpu_if->vgic_vmcr = kvm_call_hyp_ret(__vgic_v3_read_vmcr);
}

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vgic_v4_configure_vsgis()

void vgic_v4_configure_vsgis

(

struct kvm *

kvm

)

Definition at line 187 of file vgic-v4.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    struct kvm_vcpu *vcpu;
    unsigned long i;
 
    lockdep_assert_held(&kvm->arch.config_lock);
 
    kvm_arm_halt_guest(kvm);
 
    kvm_for_each_vcpu(i, vcpu, kvm) {
        if (dist->nassgireq)
            vgic_v4_enable_vsgis(vcpu);
        else
            vgic_v4_disable_vsgis(vcpu);
    }
 
    kvm_arm_resume_guest(kvm);
}

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vgic_v4_get_vlpi_state()

void vgic_v4_get_vlpi_state	(	struct vgic_irq *	irq,
		bool *	val
	)

Definition at line 213 of file vgic-v4.c.

{
    struct its_vpe *vpe = &irq->target_vcpu->arch.vgic_cpu.vgic_v3.its_vpe;
    int mask = BIT(irq->intid % BITS_PER_BYTE);
    void *va;
    u8 *ptr;
 
    va = page_address(vpe->vpt_page);
    ptr = va + irq->intid / BITS_PER_BYTE;
 
    *val = !!(*ptr & mask);
}

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vgic_v4_init()

int vgic_v4_init

(

struct kvm *

kvm

)

vgic_v4_init - Initialize the GICv4 data structures @kvm: Pointer to the VM being initialized

We may be called each time a vITS is created, or when the vgic is initialized. In both cases, the number of vcpus should now be fixed.

Definition at line 239 of file vgic-v4.c.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    struct kvm_vcpu *vcpu;
    int nr_vcpus, ret;
    unsigned long i;
 
    lockdep_assert_held(&kvm->arch.config_lock);
 
    if (!kvm_vgic_global_state.has_gicv4)
        return 0; /* Nothing to see here... move along. */
 
    if (dist->its_vm.vpes)
        return 0;
 
    nr_vcpus = atomic_read(&kvm->online_vcpus);
 
    dist->its_vm.vpes = kcalloc(nr_vcpus, sizeof(*dist->its_vm.vpes),
                    GFP_KERNEL_ACCOUNT);
    if (!dist->its_vm.vpes)
        return -ENOMEM;
 
    dist->its_vm.nr_vpes = nr_vcpus;
 
    kvm_for_each_vcpu(i, vcpu, kvm)
        dist->its_vm.vpes[i] = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;
 
    ret = its_alloc_vcpu_irqs(&dist->its_vm);
    if (ret < 0) {
        kvm_err("VPE IRQ allocation failure\n");
        kfree(dist->its_vm.vpes);
        dist->its_vm.nr_vpes = 0;
        dist->its_vm.vpes = NULL;
        return ret;
    }
 
    kvm_for_each_vcpu(i, vcpu, kvm) {
        int irq = dist->its_vm.vpes[i]->irq;
        unsigned long irq_flags = DB_IRQ_FLAGS;
 
        /*
         * Don't automatically enable the doorbell, as we're
         * flipping it back and forth when the vcpu gets
         * blocked. Also disable the lazy disabling, as the
         * doorbell could kick us out of the guest too
         * early...
         *
         * On GICv4.1, the doorbell is managed in HW and must
         * be left enabled.
         */
        if (kvm_vgic_global_state.has_gicv4_1)
            irq_flags &= ~IRQ_NOAUTOEN;
        irq_set_status_flags(irq, irq_flags);
 
        ret = vgic_v4_request_vpe_irq(vcpu, irq);
        if (ret) {
            kvm_err("failed to allocate vcpu IRQ%d\n", irq);
            /*
             * Trick: adjust the number of vpes so we know
             * how many to nuke on teardown...
             */
            dist->its_vm.nr_vpes = i;
            break;
        }
    }
 
    if (ret)
        vgic_v4_teardown(kvm);
 
    return ret;
}

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vgic_v4_request_vpe_irq()

int vgic_v4_request_vpe_irq	(	struct kvm_vcpu *	vcpu,
		int	irq
	)

Definition at line 226 of file vgic-v4.c.

{
    return request_irq(irq, vgic_v4_doorbell_handler, 0, "vcpu", vcpu);
}

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vgic_v4_teardown()

void vgic_v4_teardown

(

struct kvm *

kvm

)

vgic_v4_teardown - Free the GICv4 data structures @kvm: Pointer to the VM being destroyed

Definition at line 315 of file vgic-v4.c.

{
    struct its_vm *its_vm = &kvm->arch.vgic.its_vm;
    int i;
 
    lockdep_assert_held(&kvm->arch.config_lock);
 
    if (!its_vm->vpes)
        return;
 
    for (i = 0; i < its_vm->nr_vpes; i++) {
        struct kvm_vcpu *vcpu = kvm_get_vcpu(kvm, i);
        int irq = its_vm->vpes[i]->irq;
 
        irq_clear_status_flags(irq, DB_IRQ_FLAGS);
        free_irq(irq, vcpu);
    }
 
    its_free_vcpu_irqs(its_vm);
    kfree(its_vm->vpes);
    its_vm->nr_vpes = 0;
    its_vm->vpes = NULL;
}

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vgic_write_guest_lock()

static int vgic_write_guest_lock ( struct kvm *  kvm, gpa_t  gpa, const void *  data, unsigned long  len  )

inlinestatic

Definition at line 135 of file vgic.h.

{
    struct vgic_dist *dist = &kvm->arch.vgic;
    int ret;
 
    dist->table_write_in_progress = true;
    ret = kvm_write_guest_lock(kvm, gpa, data, len);
    dist->table_write_in_progress = false;
 
    return ret;
}

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